Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards

Hello,

I am graduate student in the Dept. of Computer Sc. & Engg. in USF. We are using a Digilent XUP2vpPro board for one of our research projects. I am trying to interface a Kingston 512 MB DDR RAM in DIMM to Xilinx virtex 2 Pro FPGA. The DDR RAM is the same that is recommended at the board's webpage. I am using the MIG 007 tool to generate the memory controller and modify it according to our needs.

I was looking for some specifications of the DDR RAM like number of banks, # of row and column address counts. I was curious if there are any specification docs that lists these details from Kingston?

Also since the DDR Memory is from a third party, xilinx does not provide any simulation libraries (like it does for BRAM's for eg). Hence the only way to do a system level simulation is either testing "on-board" or using ChipScope Pro. I was curious if RTL level models or simulation libraries are provided for these DDR RAMs so that I could do a system simulation from inside ISE itself?

If any reference designs are avialable for the memory controllers for DDR RAMs for interfacing to Xilinx V2P, that would be greatly helpful as well.

Any sort of tips/suggestion will be very helpful.

Thanks, Koustav

You can see what parts are on the DIMM (e.g., Micron, Infineon) and then figure out what the row size is from that. You can also get good HDL simulation models from Micron. They are somewhat slow, but accurate. You instantiate one DRAM model for each DRAM chip on the DIMM.

-Kevin

I think you generally have two decent options here. The cheapest is to get hold of the EDK. (Since you are associated with a university you should be able to get it very cheap. Or you might already have it.) That is by far the easiest method to get the DDR ram interface up and running on that board.

Otherwise you could take a look at the Memory interface generator at xilinx.com (aka MIG). This doesn't look to be nearly as easy to get up and running but might be an idea if you don't have the EDK or if you really cannot use the OPB or PLB bus protocol.

Finally, you could roll your own, I wouldn't recommend it though since it will probably take you a lot of time to get right. There are some open source DDR controllers available which you might be able to modify, like the one at opencores. However, at least the opencores one hasn't worked very well for me unfortunately.

Anyway, unless your purpose is to do research on the memory controller, my advice is to use the EDK's memory controller. You will be able to get the board up and running with an example running in about an hour if you have a tutorial to follow.

/Andreas

Following up to second the recommendation on the Micron datasheets and models, though they seem to omit VHDL models for some newer devices. Hynix cover that base though.

If you can't find the info you need from Kingston, why not go to Micron/Crucial for the DIMM itself? Micron fully specify them, and Crucial sell them online ... I have seen DIMMs with a Micron label on one side and a Crucial label on the other...

- Brian

Hi all,

As I can see most of you are suggesting the use of EDK for memory DDR access.

But Is there any way to combine some hardware coded in VHDL from ISE and memory controller using EDK

so these two work together to acheive the desired functionality.

its like edk memory controller reads data from ddr and gives it to the FPGA and fpga processes the information and produces the result.

thanks for your reply.

Mahalingam

Hello Brian,

We are trying to figure ot whether we should go for a EDK based ucontroller (PPC acting as a memory controller and interfacing with the other ASIC on FPGA) or generate it with the MIG based tool. But in any ways I would need simulation libraries/ RTL models for the DIMM and the DRAMs. As you suggested micron/crucial libraries would be useful. Can you provide some more information on these? (links etc). I would appreciate some docs on the DIMM architecture as well. I have e-mailed Kingston for some specification docs which lists bank #, column/row address #, and rank organization. I think I have to get into these details first as well.

Eagerly awaiting a reply.

Thanks, Koustav

Hello Andreas,

I would be grateful if you could provide me with your DDR controller and I can tailor it to my needs. I guess since you have done it this way I would try to give it a shot by going your way. Also any ideas about simulation libraries for DIMM and DRAMs ? How did you simulate ur design using DDR controllers? I am using a Kingston

Thanks again for your reply,

Koustav