Hi all,
I was wondering if there is such a thing available? I found a few free and commercial tools to edit/create bubble diagrams, which would then generate VHDL code, but I would like to be able to generate a FSM diagram from the code...
Thanks, /Mikhail
The quartus state machine viewer can do it.
-- Mike Treseler
Thanks Mike. Do you know if the viewer is included in the web(free) edition? It is not clear from the editions' comparison at the Altera web site:
/Mikhail
It's included, but won't run without a license. What doesn't show in the .pdf is that the diagram is interactive with the HDL viewer and hierarchy list. I can click on any yellow schematic block to see the state diagram, click any arrow and see the equation, click on the hierarchy list and locate the code, etc.
-- Mike Treseler
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