Kislo wrote: "When i try to simulate a coregen generated single port ram, i get a error from modelsim :
# -- Loading package blkmemsp_pkg_v6_2 # -- Loading entity blkmemsp_v6_2 # ** Error: ram.vhd(112): Internal error: ../../../src/vcom/ genexpr.c(5483) # ** Error: ram.vhd(112): VHDL Compiler exiting # ** Error: D:/modelsimXE/win32xoem/vcom failed.
what can be the cause of the error ? i can simulate async fifo, and have the newest upgrades/service packs.
from google search i found a guy hav "jedenfalls war das problem, dass die generics nur im mapping aufgef=FChrt waren und nicht im deklarationsteil der architecture des von coregen generierten files. das sollte, nein das muss man von hand =E4ndern und alles ist gut :o)"
what is it exatly i am supposed to do to get it to work ?"
Hej till Danskland.
Please bear in mind that even though the error message which Seb reported is identical to yours, it seems that it could result from many different errors. Anyway, I will try to translate Seb's tips from pseudoGerman to actual English for you, and hopefully you will not need any more help.
"jedenfalls war das problem, dass die generics nur im mapping aufgef=FChrt waren und nicht im deklarationsteil der architecture des von coregen generierten files."
Anyway the problem was, that the generics were just in the mapping (maybe he meant portmaps... I do not use Coregen, you figure it out!), and not in the declarative part of the architecture of the files generated by Coregen.
" das sollte, nein das muss man von hand =E4ndern und alles ist gut :o)"
So that should, no, that must, be modified by hand and everything will be fine.
Also, you edited out Seb's previous two pseudo-sentences which may also be useful: "es lag nicht an den libraries."
The problem was not in the libraries.
" hatte auch noch nen syntaxfehler drin
- die gutan alten semikolons :o)"
I had a few syntax errors in there - the good old semicolons.
Regards, Colin Paul Gloster