I created vhdl model of risc processor. During simulation it works correctly, but when I programmed and run it on FPGA Cyclone device, it didn't work. So I applied some signals in SignalTap Analyzer (without changing vhdl code), and it started work properly. I know that problem description is general, but maybe someone can give me some hint, what can be wrong, or what should I look for.
Thanks in advice.