Hello,
I created vhdl model of risc processor. During simulation it works correctly, but when I programmed and run it on FPGA Cyclone device, it didn't work. So I applied some signals in SignalTap Analyzer (without changing vhdl code), and it started work properly. I know that problem description is general, but maybe someone can give me some hint, what can be wrong, or what should I look for.
Thanks in advice.
I have been getting the same type of problems, but my target fails. What I have run into are adding signals to some test points. When I do this operations fail. When I remove them it works. I currently have a problem which I can't fix. I have some VHDL code which is an address decoder and it worked in the target. I added some more registers to decode and now I can't get it to work at all.
I wonder if they are some how related?
Rob
Both feel like timing problems. Synchronize to a single clock. Check static timing.
-- Mike Treseler
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