Symon,
As much as I'd like to say "great answer"! I am concerned that this particular IO standard has been characterized for a Vcco of 3.3 volts, and he won't be simulating what he wants.
By that, I mean that the IBIS file is derived from spice simulations done on the IOB at 3.3 volts, LVCMOS 24 mA. Just because he is now using the IO as pull down only, at 1.8 volts, doesn't seem to me to "match" the conditions used for the simulations.
Specifically, the dV/dt listed in the IBIS file was derived under different conditions.
Probably the difference will not be more than 10%, or perhaps even less than the slow/weak fast/strong IBIS corners.
If he had access to an hspice license, he could also download the encrypted hspice IO models, which he can then have more control of (I believe). Since it is Saturday, and I am not at Xilinx, I am unable to offer running a "what if" for Mr Test01. Perhaps when I get back in on Tuesday, (Monday is a holiday here).
Botton line? Sounds like our 'test" fellow is doing some weird and unusual stuff (which is just fine), but he may have to try it to see what he gets.
For example, it was already mentioned that if one IO doesn't slew/drive enought, put two in parallel. If that doesn't do it, put three in parallel. You may do this without concern (up to the SSO limits), as the IO is CMOS, and paralleling FETs works. The time difference between signals arriving at the IOs, and IO pins is ~ 10 ps from one IO to an adjacent IO, so he really doesn't care about non-simultaneous drive. If he is really picky, he can "see" the wire in the package from the bump to the pad in the package by selecting his package in the IBIS model. Then he could synchonize all the IO signal to arrive at the same instant externally by adding a variable length of pcb trace to each IO to make tham all the "same". We only get down to +/- 5ps accuracy for these numbers, so that exercise is hardly worth it in a small device, but for a 1136, or 1704 pin package, there can be as much as 1.5 inches from the bump to the pad in the package. So some IOs get out in .2 inches, and some get out much later. Hence the reason why a 800 Mb/s DDR interface might want to have all the IOs in a bus equal length to the sink/source.
He may want to look at the LVCMOS 1.8 V IBIS. In fact, if he instantiates LVCMOS 24 mA driver (even though it is a 3.3 V Vcco bank), I suspect that he will get a DRC warning (not an error), and he may go ahead and generate a bitstream anyway. That way, the pull down transistor "believes" it is in a 1.8 V system, and the dV/dt for that standard in the IBIS file is more accurate....if the software won't let him do this (as there are other 3.3V standards in the same bank), then I think you can turn off DRC (highly not-recommended unless you know what you are doing).
Other than my concerns, "great answer!"
Austin