Best way of moving paralell bits of data from over clock domains?

Question

What is the best way to move paralell bits of data over two clock domains inside an xilinx FPGA (Spartan-3E) to avoid meta stability?

By paralell bits i mean for example 10 x 16 bits of data collected from 10

16-bit AD converters in one clock domain which have to be moved to en different clock domain (of higher frequency).

What about dual port RAM, are they safe?

Or should i clock all data individually through two d-flipflops in series which are clocked by the second clock?

Andrew Holme · Accepted Answer

Yes, make a FIFO. This is the standard way to do it. Use the Coregen Wizard.

No, that won't work. Each bit will have a slightly different setup time, because no two path delays will be equal. You'll get bits from word [n-1] mixed with bits from word [n].

Peter Alfke · Answer

Have  a look at myTechXclusives article of 2001 on crossingasynchronous clock domains. for the insanely long URL.You do not need a FIFO (which would work fine) if, as you say, thereceiving clock is faster than the sending clock.But you must have a reasonably delayed "READY" signal that indicatesvalid data. Then you just need a control handshake with the fasterreceive clock domain.Peter Alfke

Best way of moving paralell bits of data from over clock domains?

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