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Best way of moving paralell bits of data from over clock domains?

What is the best way to move paralell bits of data over two clock domains inside an xilinx FPGA (Spartan-3E) to avoid meta stability?

By paralell bits i mean for example 10 x 16 bits of data collected from 10

16-bit AD converters in one clock domain which have to be moved to en different clock domain (of higher frequency).

What about dual port RAM, are they safe?

Or should i clock all data individually through two d-flipflops in series which are clocked by the second clock?

Reply to
Daf
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Yes, make a FIFO. This is the standard way to do it. Use the Coregen Wizard.

No, that won't work. Each bit will have a slightly different setup time, because no two path delays will be equal. You'll get bits from word [n-1] mixed with bits from word [n].

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Andrew Holme

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Peter Alfke

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