Best way of moving paralell bits of data from over clock domains?

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What is the best way to move paralell bits of data over two clock domains
inside an xilinx FPGA (Spartan-3E) to avoid meta stability?

By paralell bits i mean for example 10 x 16 bits of data collected from 10
16-bit AD converters in one clock domain which have to be moved to en
different clock domain (of higher frequency).

What about dual port RAM, are they safe?

Or should i clock all data individually through two d-flipflops in series
which are clocked by the second clock?



Re: Best way of moving paralell bits of data from over clock domains?

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Yes, make a FIFO.  This is the standard way to do it.  Use the Coregen
Wizard.

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No, that won't work.  Each bit will have a slightly different setup time,
because no two path delays will be equal.  You'll get bits from word [n-1]
mixed with bits from word [n].



Re: Best way of moving paralell bits of data from over clock domains?
Have  a look at myTechXclusives article of 2001 on crossing
asynchronous clock domains.
http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&category=-19240&sGlobalNavPick=SUPPORT&sSecondaryNavPick=&multPartNum=1&sTechX_ID=pa_clock_bound
Sorry for the insanely long URL.
You do not need a FIFO (which would work fine) if, as you say, the
receiving clock is faster than the sending clock.
But you must have a reasonably delayed "READY" signal that indicates
valid data. Then you just need a control handshake with the faster
receive clock domain.
Peter Alfke

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