Field-Programmable Gate Arrays

Can't get AREA_GROUP to work

I am trying to use area_group in my constraints file, but I keep getting the error ERROR:NgdBuild:753 - "constraints.uc...

2 comments posted 19yrs

posted by javaguy11111

2 comments posted 19yrs posted by javaguy11111

Seeing DCM LOCKED getting asserted in simulation at the same time CLKDV and CLKFX/CLKFX180 begin toggling

I'm simulating a DCM using Aldec Active-HDL 7.2 with Xilinx ISE 8.2i SP3 simulation libraries and I'm seeing LOCKED get...

1 comments posted 19yrs

posted by bwilson79

1 comments posted 19yrs posted by bwilson79

Spartan 3E Starter Kit and EDK 8.2

Hi, I'm trying to build and test a simple project for Spartan 3E Starter Kit rev D (S3ESK) board using Xilinx EDK tool...

1 comments posted 19yrs

posted by thomas.b36

1 comments posted 19yrs posted by thomas.b36

Chain of LUTs is being removed during par

Hi, I want to test what kind of delay is introduced by having an input go through 1000 LUT1 primitive in a Spartan3E FP...

4 comments posted 19yrs

posted by axr0284

4 comments posted 19yrs posted by axr0284

Ise Flow with PowerPC

Hi, I am very interesting in how could I use ISE to create a PowerPC model. I know that there is a Export to Project Na...

4 comments posted 19yrs

posted by pbantunez

4 comments posted 19yrs posted by pbantunez

180 differential inputs each 800Mbps using V5

We have an application where I need to feed 160 differential data inputs and 20 differential clock inputs to the high e...

22 comments posted 19yrs

posted by cpandya

22 comments posted 19yrs posted by cpandya

Building Gradually Expertise on VHDL/Verilog Design

Hi, i have been reading the VHDL language over the last week and now i want to put what i have learned so far into prac...

3 comments posted 19yrs

posted by DGerimi

3 comments posted 19yrs posted by DGerimi

ANNC: Secure FPGA Configuration Over Ethernet Webcast

Lattice is holding a webcast tomorrow, Thursday, May 31, "Secure FPGA Configuration Over Ethernet," covering a Verilog...

0 comments posted 19yrs

posted by bart.borosky

0 comments posted 19yrs posted by bart.borosky

XS40 Download Cable

Dear Folks ! I'm hvin a rather outdated XS40 board, which I'm planning to start experiment with. Unfortunately, I don't...

2 comments posted 19yrs

posted by raxpeter

2 comments posted 19yrs posted by raxpeter

Virtex4 Configuration Problem

Hello, I'm trying to use a slightly unconventional way of configuring a Xilinx Virtex4 FPGA that as far as I can tell s...

2 comments posted 19yrs

posted by msn444

2 comments posted 19yrs posted by msn444

Spartan-3E DIG-3E1600 Development Board Kit

Hi, I wonder if someone know where I can buy the "Spartan-3E DIG-3E1600 Development Board Kit" http://www.digilentinc.c...

6 comments posted 19yrs

posted by sdroamt

6 comments posted 19yrs posted by sdroamt

Nexys by Digilen xbd file

Hi, I recently got a nexys -1000 board for a project i'm working on and would like to put a xilinx EDK design on the bo...

15 comments posted 19yrs

posted by godzillalad

15 comments posted 19yrs posted by godzillalad

Xilinx CIC core in Spartan 3?

Does anyone know if the Xilinx CIC core will work in the Spartan 3? It's not listed as a target (only Spartan IIE) but t...

1 comments posted 19yrs

posted by cs_posting

1 comments posted 19yrs posted by cs_posting

Help: Best use of DCM in Spartan-3A?

For my design I must use two DCMs in series. How do I best use the CLKIN, RST, CLKFX and the LOCKED pin of the DCM? Sho...

5 comments posted 19yrs

posted by tool

5 comments posted 19yrs posted by tool

what is register packing?

I am reading Cyclone II device handbook. A concept, register packing confuses me. I know if we use the LUT and register...

2 comments posted 19yrs

posted by dechenxu

2 comments posted 19yrs posted by dechenxu