I'm simulating a DCM using Aldec Active-HDL 7.2 with Xilinx ISE 8.2i SP3 simulation libraries and I'm seeing LOCKED getting asserted at exactly the same time my CLKDV, CLKFX, and CLKFX180 output begin toggling. According to the Virtex-4 User Guide, the DCM output clocks are invalid until LOCKED is asserted. However, this is not what I'm seeing in simulation. Does this sound like a simulation model error or is this the actual behavior I will see in the hardware. I want to use the inverse of LOCKED as a reset for the upstream logic to guarantee it is held in reset until all the clocks are valid.
15 years ago