Latest threads in Field-Programmable Gate Arrays

Problem with System ACE

Hi folks, I am desperately trying to load a design via System ACE onto a ML403 board. What I use: ISE 8.2i ML403 Linux...

1 19yrs

hachti

1 19yrs hachti

Create and Import Peripheral in EDK

Hello everybody, I am trying to interface my user logic ip_inv through the OPB in EDK using a register like this: the c...

1 19yrs

koustav79

1 19yrs koustav79

Synchronization of instruction with clock

we are making bram controller which takes instruction from microblaze processor.we have to write a c program giving rea...

0 19yrs

kahnani

0 19yrs kahnani

Altera Serial Flash Loader (SFL) question

I just found the Serial Flash Loader (SFL) which allows you to program an Active Serial (AS) part (EPCSx) using the JTA...

4 19yrs

ben

4 19yrs ben

Microcontrollers have a better predictable time behaviour than FPGAs

"Microcontrollers have a better predictable time behaviour, because their circuit is integrated in silicon and is uncha...

8 19yrs

jidan1

8 19yrs jidan1

Raggedstone1 Brackets

For those of you that were desperate for Raggedstone1 brackets we finally have them in stock. They won't show as stock...

0 19yrs

g1

0 19yrs g1

ngdbuild error : multiple drivers and driving non buffer primitives

Dear all, i am trying to implement a memory controller and am getting the following errors during translate. i wud grea...

6 19yrs

mahalingamv

6 19yrs mahalingamv

FIFO : Synchronous WRITE, Asynchronous READ ?

Hi I have problem to implement a FIFO with "Synchronous WRITE, Asynchronous READ" in Xilinx device. Since the FIFO size...

11 19yrs

pasacco

11 19yrs pasacco

Xilinx OPB External Memory Controller

I have a system on a Virtex4-FX with a MicroBlaze and the xilinx opb_emc (v 2.00). I thought I set up the parameters pr...

4 19yrs

morphiend

4 19yrs morphiend

LocalLink TEMAC Data Corruption

I have a design using the MPMC2 with a PowerPC and a CDMAC w/ LocalLink TEMAC on a Virtex4-FX. On the ppc I have Linux...

4 19yrs

morphiend

4 19yrs morphiend

How to execute application code out of external memory using EDK?

Dear All, Since the program cannot fit in an internal ram, I have to use external memory, such as ddr. As Xilinx edk in...

1 19yrs

yao.sics

1 19yrs yao.sics

What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?

I've been looking at the various core/macro generators and they all seem horribly large and slow, almost like student d...

10 19yrs

air_bits

10 19yrs air_bits

Weekend pop quiz

A memory block has been told having "read latency of 3", assume the read pointer has been reset How many read clocks do...

6 19yrs

ccon67

6 19yrs ccon67

Tristate ipcore problem with XPS

We are trying to build an ipcore in XPS. Based on the vhdl code we got from digilent's site, we are trying to interface...

0 19yrs

nkubiak

0 19yrs nkubiak

xilinx parallel cable troubles

Like so many who've come before more me I'm having problem getting th Xilinx Parallel Port cable to work. I know there'...

6 19yrs

lgs23

6 19yrs lgs23

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