Field-Programmable Gate Arrays

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Synchronization of instruction with clock

we are making bram controller which takes instruction from microblaze processor.we have to write a c program giving rea...
0 comments posted 19yrs
posted by kahnani
0 comments posted 19yrs posted by kahnani

Altera Serial Flash Loader (SFL) question

I just found the Serial Flash Loader (SFL) which allows you to program an Active Serial (AS) part (EPCSx) using the JTA...
4 comments posted 19yrs
posted by ben
4 comments posted 19yrs posted by ben

Raggedstone1 Brackets

For those of you that were desperate for Raggedstone1 brackets we finally have them in stock. They won't show as stock...
0 comments posted 19yrs
posted by g1
0 comments posted 19yrs posted by g1

FIFO : Synchronous WRITE, Asynchronous READ ?

Hi I have problem to implement a FIFO with "Synchronous WRITE, Asynchronous READ" in Xilinx device. Since the FIFO size...
11 comments posted 19yrs
posted by pasacco
11 comments posted 19yrs posted by pasacco

Xilinx OPB External Memory Controller

I have a system on a Virtex4-FX with a MicroBlaze and the xilinx opb_emc (v 2.00). I thought I set up the parameters pr...
4 comments posted 19yrs
posted by morphiend
4 comments posted 19yrs posted by morphiend

LocalLink TEMAC Data Corruption

I have a design using the MPMC2 with a PowerPC and a CDMAC w/ LocalLink TEMAC on a Virtex4-FX. On the ppc I have Linux...
4 comments posted 19yrs
posted by morphiend
4 comments posted 19yrs posted by morphiend

Weekend pop quiz

A memory block has been told having "read latency of 3", assume the read pointer has been reset How many read clocks do...
6 comments posted 19yrs
posted by ccon67
6 comments posted 19yrs posted by ccon67

Tristate ipcore problem with XPS

We are trying to build an ipcore in XPS. Based on the vhdl code we got from digilent's site, we are trying to interface...
0 comments posted 19yrs
posted by nkubiak
0 comments posted 19yrs posted by nkubiak

xilinx parallel cable troubles

Like so many who've come before more me I'm having problem getting th Xilinx Parallel Port cable to work. I know there'...
6 comments posted 19yrs
posted by lgs23
6 comments posted 19yrs posted by lgs23

Modular Design Example

Is there an example of a modular design project for ISE that I can download. I could not find one on the xilnx website...
1 comments posted 19yrs
posted by javaguy11111
1 comments posted 19yrs posted by javaguy11111