Field-Programmable Gate Arrays

Bootloader in BRAM to run a program loaded in the DDR

Hi, I want to ask if it is possible to load a program in the BRAM able to run another main program (with PowerPC) in th...

3 comments posted 19yrs

posted by pbantunez

3 comments posted 19yrs posted by pbantunez

Cyclone 3 Starter Board connector?

The Cyclone 3 Starter Board has this strange "High-Speed Mezzanine Connector (HSMC)". I'd prefer something simpler, such...

0 comments posted 19yrs

posted by pkk

0 comments posted 19yrs posted by pkk

CoreGen Issues ??

Has anyone seen an issue with the CoreGenerater that when I try and generate some of the cores I get a "corrupted" dial...

1 comments posted 19yrs

posted by xx

1 comments posted 19yrs posted by xx

ise9.1 : partitions with edif flow

I would like to use partitions with the edif flow. I'm using an older version of SynplifyPro which does not support par...

4 comments posted 19yrs

posted by tmorlion

4 comments posted 19yrs posted by tmorlion

using ICAP with the ML310

Hi there, I am trying to use the ICAP module of my Virtex II Pro. I built a project with EDK8.1, but when executing the...

3 comments posted 19yrs

posted by fabien.goy

3 comments posted 19yrs posted by fabien.goy

Regarding multiple write problem in opencores pci bridge

Hello there, I have been using opencores PCI core and its working very fine. If someone has already used it please clar...

1 comments posted 19yrs

posted by madnan.rashid

1 comments posted 19yrs posted by madnan.rashid

Virtex-4 troubles after configuration

Hi everybody, After successfull configuration of a Virtex-4 my design has troubles. But if I reconfigure using the same...

0 comments posted 19yrs

posted by taileb.mehdi

0 comments posted 19yrs posted by taileb.mehdi

Xilinx MIG and verifying UCF files

Hi, I just started to use the Xilinx Memory Interface Generator 1.72 and ran into some problems when veryfying the UCF...

1 comments posted 19yrs

posted by sheinzle

1 comments posted 19yrs posted by sheinzle

Some doubts in the FPGA design flow in the ISE

Hi, I am not been able to understand the details of the each stage in the design flow. Actually what are the things hap...

1 comments posted 19yrs

posted by subin.82

1 comments posted 19yrs posted by subin.82

Can anyone explain the details of the FPGA design flow in ISE

Hi, I know the the fpga design flow in the ISE tool. But i like to know in more details about the process that takes pla...

3 comments posted 19yrs

posted by subin.82

3 comments posted 19yrs posted by subin.82

Actel Cortex M1, any info on license fee?

Actel is known lying before, they namly claimed that the use of ARM7 in Actel FPGA is free, actually the FPGA with AES1...

2 comments posted 19yrs

posted by Antti.Lukats

2 comments posted 19yrs posted by Antti.Lukats

s3 starterkit problem

Hi after adding just one GPIO to Xilinx spartan-3A webserver demo design, the system started to fail everything starts...

0 comments posted 19yrs

posted by Antti.Lukats

0 comments posted 19yrs posted by Antti.Lukats

After PAR simulation, should I assume that it will work on FPGA board?

Hi, I am using ML403 board consisting of Virtex-4 device. I have simulated my design on ISE 8.1i. I completed simulatio...

4 comments posted 19yrs

posted by sandip.gaikwad

4 comments posted 19yrs posted by sandip.gaikwad

FIR ON FPGA

Hi, I'm working on implementing an FIR Filter on a FPGA (Spartan 3E), here's what i want to accomplish --> The FIR Filt...

5 comments posted 19yrs

posted by bngguy

5 comments posted 19yrs posted by bngguy

Cyclone 3 Starter Board Question

Anyone know how the USB Blaster cable loads data to the C3 fpga on the board? The schematic shows a CPLD between the FP...

8 comments posted 19yrs

posted by fpgabuilder-groups

8 comments posted 19yrs posted by fpgabuilder-groups