I have a system on a Virtex4-FX with a MicroBlaze and the xilinx opb_emc (v 2.00). I thought I set up the parameters properly to match the async FLASH memory chip that I have on my development board, but the controller does not look to be respecting the settings I set.
I have the system running at 100MHz, and the external FLASH chip is a
70ns Spansion part. On a read, the address needs to stay valid for 70ns, but it's only staying valid for ~2 cycles (where the cycles are based upon the 100MHz clock, and observed using ChipScope). The same happens for a write, for say putting the chip into CFI mode, the write line is only staying asserted for ~2 cycles when it needs to be 70ns as well.I tried increasing the timespec values for the ipcore, but the external operation stayed exactly the same even if I doubled the requirements.
Has anyone seen or experienced similar problems?
TIA,
Mike Koss