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ngdbuild error : multiple drivers and driving non buffer primitives

Dear all,

i am trying to implement a memory controller and am getting the following errors during translate.

i wud greatly appreciate if u cud provide some comments/suggestions.

thanks,. Mahalingam

Process "Synthesize" completed successfully Started : "Translate". Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc mem_interface_top.ucf -p xc2vp30-ff896-7 testbench.ngc testbench.ngd Reading NGO file 'C:/Xilinx/memory_interface_koustav/ testbench.ngc' ... Applying constraints in "mem_interface_top.ucf" to the design... Checking timing specifications ... Checking expanded design ... WARNING:NgdBuild:440 - FF primitive 'mymeminttop/ddr1_top0/controller0/ACK_REG_INST1' has unconnected output pin ERROR:NgdBuild:924 - input pad net 'myclk' is driving non-buffer primitives: pin C on block my_user_command_register_1 with type FDE, pin C on block my_user_command_register_2 with type FDE, pin C on block my_led_error_output with type FDE, pin C on block tmp_user_config_register_1 with type FDE, pin C on block init_count2_0 with type FDE, pin C on block init_count2_1 with type FDE, pin C on block init_count2_2 with type FDE, pin C on block init_count2_13 with type FDE, pin C on block init_count2_14 with type FDE, pin C on block init_count2_15 with type FDE WARNING:NgdBuild:483 - Attribute "IOSTANDARD" on "led_error_output" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute. WARNING:NgdBuild:483 - Attribute "LOC" on "led_error_output" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute. ERROR:NgdBuild:455 - logical net 'myclknot' has multiple driver(s): pin O on block myclknot1_INV_0 with type INV, pin PAD on block myclknot with type PAD ERROR:NgdBuild:925 - input net 'myclknot' is connected to the incorrect side of buffer(s): pin O on block myclknot1_INV_0 with type INV

NGDBUILD Design Results Summary: Number of errors: 3 Number of warnings: 3

One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "testbench.bld"... Process "Translate" failed

Reply to
mahalingamv
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I think it looks like your clock input it directly connected from the input pad to logic. You need to first connect it to some type of global clock buffer or other clock resource before using it in the fabric.

And it looks like you have placed constraints incorrectly for the led_error_output. It should be an ouput signal at your top level. Then the syntax in the UCF is:

NET "led_error_output" LOC = "whatever" | IOSTANDARD = "whatever" ;

Reply to
motty

hey motty,

i tried connecting it the port myclk to a temproary signal and then to the fabtric, did not work.

secondly. tried placing a bufg component in between port myclk and mynewclk and the error is still the same

thanks a lot for your help newayz.

still breaking my head on it

regards, Mahalingam

Reply to
mahalingamv

Have you checked the source of "myclknot"? Seems like it is being driven by a pad AND by logic.

cu, Seam

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Reply to
Sean Durkin

Are you doing this in Verilog or VHDL? Can you post your code (or the important part with the clock) so we can see what's going on? Is 'myclk' input to a clock pad or just a regular I/O?

Reply to
motty

Needs an ibufg, not a bufg component.

Or an ibuf followed by a bufg; the ibufg is just shorthand for these two.

- Brian

Reply to
Brian Drummond

hi all,

thanks very much for your responses.

port myclk2 : in std_logic

it is connected to the system clock in the ucf file.

my current code in vhdl looks like this.

g1: ibufg (myclk2, myclk);

myclknot

Reply to
mahalingamv

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