Field-Programmable Gate Arrays

How can i convert char* / string to sc_lv<16> ?

Hello, i am beginner in SystemC and have to programm a lawa simulation. My Problem is, i have to read the commands from...

0 comments posted 19yrs

posted by taner.cosar

0 comments posted 19yrs posted by taner.cosar

Symbolic names for pll derived clocks in SDC file? (quartus)

Hi All, I'm synthesizing the IP core for my chip using the Altera Quartus tools. When I define constraints in the SDC f...

4 comments posted 19yrs

posted by wzab

4 comments posted 19yrs posted by wzab

What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)

Hoping that the dynamic constant multiplier could save numbers of CLBs, but it's contrary. So, what's the use of it if...

5 comments posted 19yrs

posted by ccon67

5 comments posted 19yrs posted by ccon67

Lattce SC Purspeed I/O

The Lattice SC purespeed I/O supports 2 Gbps data rate. This is the maximum available data rate in parallel I/O - in co...

8 comments posted 19yrs

posted by dmoyes

8 comments posted 19yrs posted by dmoyes

JTAG as UART for PowerPC in XMD.

Hi, I have seen about configuring the JTAG as UART since I have not RS232 port in my board. I have found that Xilinx pr...

4 comments posted 19yrs

posted by pbantunez

4 comments posted 19yrs posted by pbantunez

verilog HDL problem

what is the error in the following code. in it the main module is "test". in that module's "always" block another modul...

2 comments posted 19yrs

posted by nasif4003

2 comments posted 19yrs posted by nasif4003

A first FPGA project

I have been trying to find the time to start a project with an FPGA for a while and I think I've finally found one. I'v...

6 comments posted 19yrs

posted by grant

6 comments posted 19yrs posted by grant

No output while booting ML403 board

Anyone, When I try to boot linux on a Xlinx ML403 board I get the following out put: loaded at: 00400000 004FA1A0 board...

2 comments posted 19yrs

posted by gseegmiller

2 comments posted 19yrs posted by gseegmiller

FPGA / Virtex II Pro / LWIP

Hi, I'd like to get some help from experienced people because I'm really running low on ideas here.. I'm a beginner in...

4 comments posted 19yrs

posted by antoine.vernay

4 comments posted 19yrs posted by antoine.vernay

How many OSERDES per bufio

It seems that bufio has the lowest clock skew in order to clock the oserdes. OSERDES in my configuration requires two c...

3 comments posted 19yrs

posted by cpandya

3 comments posted 19yrs posted by cpandya

What should be taken care of when two FPGA broad connected together?

I have two FPGA development boards, using different power source. when I connected their IO pins, should I connect the...

4 comments posted 19yrs

posted by junsong.liao

4 comments posted 19yrs posted by junsong.liao

ANNC: PCI Express Card Power Management Webcast Today

Lattice is holding a webcast today, Wednesday, June 6, "PCI Express Card Power Management." The presenter will be Jim K...

0 comments posted 19yrs

posted by bart.borosky

0 comments posted 19yrs posted by bart.borosky

Quartus Advisors

Hello, I use Altera's Quartus II software for my FPGA development and in the software package they have the following A...

1 comments posted 19yrs

posted by jjlindula

1 comments posted 19yrs posted by jjlindula

Re: data compression algorithms on FPGA

Did someone have a realistic gate count for jbig on an fgpa?

0 comments posted 19yrs

posted by daniel1000

0 comments posted 19yrs posted by daniel1000

Reg:Clock to pad Delay of the System Clock.

Hi experts, Hi all i need a help,I am using the spartan FPGA.I am using the DCM to scale the input clock frequency to 7...

0 comments posted 19yrs

posted by vlnaran

0 comments posted 19yrs posted by vlnaran