Field-Programmable Gate Arrays

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another Forth CPU design

While trying to minimize my microcode implementation to implement a small 6502 CPU, eventually I designed a new Forth C...
6 comments posted 19yrs
posted by fb
6 comments posted 19yrs posted by fb

LVPECL output skew

I would like to use Virtex5 FPGA to output 16 differential channels at 800Mbps source synchronously. I am planning to u...
15 comments posted 19yrs
posted by dmoyes
15 comments posted 19yrs posted by dmoyes

How can i convert char* / string to sc_lv<16> ?

Hello, i am beginner in SystemC and have to programm a lawa simulation. My Problem is, i have to read the commands from...
0 comments posted 19yrs
posted by taner.cosar
0 comments posted 19yrs posted by taner.cosar

Lattce SC Purspeed I/O

The Lattice SC purespeed I/O supports 2 Gbps data rate. This is the maximum available data rate in parallel I/O - in co...
8 comments posted 19yrs
posted by dmoyes
8 comments posted 19yrs posted by dmoyes

JTAG as UART for PowerPC in XMD.

Hi, I have seen about configuring the JTAG as UART since I have not RS232 port in my board. I have found that Xilinx pr...
4 comments posted 19yrs
posted by pbantunez
4 comments posted 19yrs posted by pbantunez

verilog HDL problem

what is the error in the following code. in it the main module is "test". in that module's "always" block another modul...
2 comments posted 19yrs
posted by nasif4003
2 comments posted 19yrs posted by nasif4003

A first FPGA project

I have been trying to find the time to start a project with an FPGA for a while and I think I've finally found one. I'v...
6 comments posted 19yrs
posted by grant
6 comments posted 19yrs posted by grant

No output while booting ML403 board

Anyone, When I try to boot linux on a Xlinx ML403 board I get the following out put: loaded at: 00400000 004FA1A0 board...
2 comments posted 19yrs
posted by gseegmiller
2 comments posted 19yrs posted by gseegmiller

FPGA / Virtex II Pro / LWIP

Hi, I'd like to get some help from experienced people because I'm really running low on ideas here.. I'm a beginner in...
4 comments posted 19yrs
posted by antoine.vernay
4 comments posted 19yrs posted by antoine.vernay

How many OSERDES per bufio

It seems that bufio has the lowest clock skew in order to clock the oserdes. OSERDES in my configuration requires two c...
3 comments posted 19yrs
posted by cpandya
3 comments posted 19yrs posted by cpandya

Quartus Advisors

Hello, I use Altera's Quartus II software for my FPGA development and in the software package they have the following A...
1 comments posted 19yrs
posted by jjlindula
1 comments posted 19yrs posted by jjlindula