Lattce SC Purspeed I/O

From Lattice's website,

"Another key factor in buffer performance is pin capacitance. With clock periods in the nanosecond range, rise and fall times are, to say the least, critical. If pin capacitance is too high, a major portion of the clock period will be lost due to the slow rise time, severely limiting overall buffer performance. To combat this, the LatticeSC I/O pads have reduced capacitance (see Table 1), allowing Lattice to achieve best-in-class performance of 2Gbps."

However, I think you'll find the pins don't have enough capacitance to control crosstalk. That's right, isn't it Austin? ;-)

HTH, Syms.

Symon,

Lattice has banks dedicated to just this purpose. They have limited IO standards, because the capacitance MUST be low at Gb/s data rates.

In that sense, they no longer have "all IOs equally the same."

This is a business decision: these pins can really only be used now for a much narrower range of applications, and pcb layout is constrained to always using these pins. In differentiates them from us, and that is what they need to survive (as if they go head to head, they are lost in the 'noise).

In order to stay in business, Lattice has to carefully evaluate their features, and see if they can squeeze a few percent of market share. That is just fine by us. We continue to gain market share, so it must be extremely painful for our competition. Altera has no high speed 65nm process, and are more than one year late for S3, and Lattice has a great fab partner, and some very clever and useful features, but is so small, they can't compete on IP, services, software, and all the other things that make up an ecosystem surrounding a product. They have resorted to blogging for support (which is interesting, but makes me think they have no resources to do any serious support).

If a dedicated bank, or even dedicated hard IP (which they also offer for some interfaces) looks like a great idea, then perhaps some future offering from Xilinx might have something similar. Until then...

Austin

Austin,

And that's why the big X can't still offer a high end V5 with MGT's on a low cost small footprint (like 256fpBGA), isn't it? Some customers are not so happy anymore with the model that the big ones dictate the law. This is probably the biggest reason why there will always be a place for companies like Lattice and Actel.

"...but is so small, they can't compete on IP, services, software, and all the other ..." is this your personal opinion, or is this the way that Xilinx masks that you are not capable of achieving the same performance out of a high speed process...?

And what I see (and hear) is that Lattice FAE's deliver at least the same or sometimes even better support than Xilinx's (for normal companies, not the Alcatel's and Cisco's of this world of course). I can't comment on Altera because I never used it before.

Regards,

Luc

Luc,

Do you simply have a Xilinx thorn in your side that's making you a little grumpy?

The MGTs *are* dedicated I/O standards without the "baggage" of supplying every standard known to Marketing.

There are devices that have very high speed I/O in wireframe parts. There are devices that have high speed transceivers on tiny BGAs. But how many designers - what percentage of the market - need a cutting-edge family with enormous bandwidth to be in a tiny package that rivals the size of the die?

I was in telecom years ago where the ideal chip might have 8 I/O for the system and a little more for control. They're just not made because the number of people that could use them are so small.

Since most designers can simply not use some of the many I/O available on the hyper-performance devices, how many people are truly affected by the absence of the "convenient" 256 bin BGA?

I'm also left wondering: what's the smallest flip-chip package Xilinx produces for any family?

- John_H

Luc,

There is always "room for one more."

As for what Lattice is offering, I have said it is impressive, and has some really nice features. I have also said that their fab partner is "world class" and presently on the cutting edge. How they will proceed to 45nm, and then 32nm, and so on is of course another matter altogether...

Look at Altera: they can't influence TSMC, so they have no high speed

I will venture to say that our 200 Xilinx FAEs and our 200 disti FAEs are the best in the world, and that there is no company that can even come close to our support. The experience (some 25+ SI experts), the RocketLabs (12 locations, the use of millions of dollars of equipment, combined with experts, and working designs), our 40+ MGT characterization reports for every possible standard....the list is actually too long to list here!

Not to mention, that no one has a 'Peter Alfke' (12,000 hits on Google), nor an 'Austin Lesea' (827 hits -- after all, I am still pretty much the 'baby' here at Xilinx!). We are just crazy enough to help anyone succeed (with Xilinx FPGAs).

I have in no way suggested that Lattice has any failings whatsoever, other than suffering from being small.

Personally, I love a challenge, and since Altera offers none, Lattice is welcome to join the game.

Austin

Hard IP is certainly the pathway for highest performance, so it is a question of when, not if.

FPGAs also overlap with devices like this :

For $14/10K, you get 2.5GBps PCI express, GBit Etherenet, 480 MHz USB and a 1000DMIPS PPC CPU - and if all that allows you to choose s smaller/cheaper FPGA, for 'just the programmable stuff' (it only has to save $14...), then that design combination gets traction.

-jg

John

I just have had bad experience with Xilinx. And having a small company, I was left alone 'in the dark'. Even disty didn't bother. One of the Lattice FAE's came in and het converted my design, and got it working. Therefore...

On your comment, I'm still waiting for the ideal FPGA. One power supply, a couple of inputs, a couple of outputs - that's it. Of course then the discussion starts all over again. How many in- and outputs...

That said, I like the Lattice products, the feature set serves me well. And the capabilities of the 'PureSpeed I/O's' (2Gbps) are far beyond what Xilinx can offer today - even on their 'high speed' 65nm process.

Luc

I haven't designed anything with these yet, but things that I thought looked interesting in the datasheets were :

- alternate input termination modes - termination to VTT - center tap termination

- somewhat lower Cin on the general purpose I/O than equivalent Xilinx parts

- on-chip terminations stay linear vs. input common mode voltage

- controlled slew rate drivers

IIRC, the I/O banking restrictions were mild, unless you need lots of 3.3V I/O: - differential inputs on all banks - 3.3V I/O restricted to top/bottom banks - 2.5V I/O on left/right banks - current mode output drivers left/right sides only

( most Xilinx parts require you to be in a 2.5V bank anyway for LVDS drivers and input terminations )

Brian