While trying to minimize my microcode implementation to implement a small
6502 CPU, eventually I designed a new Forth CPU:I would like to have a full Forth system for it, which could run at about 4 MIPS with a 50 MHz clock on a FPGA with internal block RAM. This could be at least doubled with some more thinking about the RAM interface. With this system I can implement a 6502 CPU emulation :-)
But first I would like to hear some comments. What do you think about the instruction set architecture (ISA)? Any ideas how to modify the VHDL code (see bottom of the page) or the ISA to use less LEs, but without impact on the compactness of code for the CPU?
At the bottom of the page you can find a full Quartus 7.1 project for testing it. Looks like adjusting some settings can increase or decrase the number of LEs by 20% and more. E.g. when changing "Auto RAM replacement" to "On" in "More Settings" in "Analysis & Synthesis Settings" increases the LE count from 590 to 697 LEs, which is strange, because I would expect that replacing registers and logic with RAM should save LEs, and if not, the compiler should not use it.
When the design is finished, I want to implement an assembler for the system in Forth. How could the mnemonics look like and are there any good examples of assemblers in Forth, which could be used to implement my ISA? For testing, an emulator would be nice, too, but this should be easy to implement, because of the simple and orthogonal ISA.