verilog HDL problem

what is the error in the following code. in it the main module is "test". in that module's "always" block another module "counter" is called. but it shows error. how can i solve the problem? how can i call another module in always block?

module counter(clock, reset, count); input clock, reset; output [3:0] count;

reg [3:0] next_count,count;

always@* begin if(count

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You can't. Try:

module test(clock,reset,count); input clock, reset; output [3:0] count; wire [3:0] count;

counter counter_inst(clock, reset, count);


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Jon Beniston

hey guys: you can't Instance any module in the procedural blocks like "always". for this work you should use Generators , but in your case as Jon Beniston wrote you don't need to use always @ clock.


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