I have two FPGAs with 4 MGTs connected between them using Aurora. The firmware guy has insisted (and I've taken a quick look myself) that we cannot define the link order. This means that I have to layout the PCB with the MGTs crossing over each other.
I can't easily ask Xilinx directly because it is the firmware guys responsibility hence my post here.
Does anyone here know whether this is definitely the case or not?
Sorry to use google to post this. I am certain that making a technical request to an admin dept run by HP in India to allow me proper usenet access will not succeed.
6 years ago