entity component binding issue with configurations

I have binding warnings
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with
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How do I solve them ? even I modify the configuration as in
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, I have this error
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Reply to
Marvin L
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The first error message: key_expansion.vhd:46:1:warning: 's0' is not bound
Line 46 looks like this: s0: subbytes port map ( sbox_in => tmp_w(23 downto 16) , sbox_out => subword(31 downto 24) );
Your component declaration looks ok (based on what I would expect subbytes to look like).
Did you remember to compile subbytes.vhd?
BTW, you can download free versions of AES crypto engine VHDL source in all shapes an sizes. Many of them will even work correctly.
Regards, Allan
Reply to
Allan Herriman
I have solved the problem. I forgot to compile subbytes.vhd and round_constant.vhd together with key_expansion.vhd but in gHDL, I open in .ghw format but I still could not view internal signals such as w0, w1, w2, w3, temp_w WHY ?
Reply to
Marvin L
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stant.vhd together with key_expansion.vhd but in gHDL, I open in .ghw form at but I still could not view internal signals such as w0, w1, w2, w3, temp _w WHY ?
I could not view the internal signal
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even th ough I am using the formal format *ghw with
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, ht tp://paste2.org/vpbvXcID ,
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,
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Reply to
Marvin L

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