entity component binding issue with configurations

The first error message: key_expansion.vhd:46:1:warning: 's0' is not bound

Line 46 looks like this: s0: subbytes port map ( sbox_in => tmp_w(23 downto 16) , sbox_out => subword(31 downto 24) );

Your component declaration looks ok (based on what I would expect subbytes to look like).

Did you remember to compile subbytes.vhd?

BTW, you can download free versions of AES crypto engine VHDL source in all shapes an sizes. Many of them will even work correctly.

Regards, Allan

I have solved the problem. I forgot to compile subbytes.vhd and round_constant.vhd together with key_expansion.vhd but in gHDL, I open in .ghw format but I still could not view internal signals such as w0, w1, w2, w3, temp_w WHY ?

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stant.vhd together with key_expansion.vhd but in gHDL, I open in .ghw form at but I still could not view internal signals such as w0, w1, w2, w3, temp _w WHY ?

I could not view the internal signal