Hi All,
I created the TimingAnalyzer a long time ago. In the years that have past, the interest in this kind of tool has decreased. I think for the following few reasons.
Engineers use tools from the vendors for timing analysis There are other tools that can be used to just draw timing diagrams.
If I continue development, I want to focus on the following:
Displaying multiple time scales in one diagram for mixed Analog and Digital diagrams Creating RTL source code from timing diagrams Creating SystemVerilog/UVM verification source doc from timing diagrams Improved VCD support Improved Python scripting support
I would appreciate your opinions and comments.
Thanks, Dan Fabrizio