The TimingAnalyzer (Timing Diagrams and Analysis)

Hi All,
I created the TimingAnalyzer a long time ago. In the years that have past, the interest in this kind of tool has decreased. I think for the following few reasons.
Engineers use tools from the vendors for timing analysis
There are other tools that can be used to just draw timing diagrams.
If I continue development, I want to focus on the following:
Displaying multiple time scales in one diagram for mixed Analog and Digital diagrams
Creating RTL source code from timing diagrams
Creating SystemVerilog/UVM verification source doc from timing diagrams
Improved VCD support
Improved Python scripting support
I would appreciate your opinions and comments.
Thanks,
Dan Fabrizio
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timinganalyzer
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What immediately comes to my mind is getting the absolute file path of the .tim file to be able to use the location of that file as storage for output from python scripts.
I use your tool quite often to build vhdl testbenches. So far I use the cpp c-pre-processor to be able to include the vhdl output of the python script into the testbench vhdl.
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Svenn
Reply to
Svenn Are Bjerkem
Ok. I will add that function to the python api. I'm glad to hear you use it for vhdl test vectors.
Thanks for your feedback, Dan
Reply to
timinganalyzer
Hi Svenn,
I recently released a new version of the TimingAnalyzer that includes the p ython function you requested. I'm also working on creating cycle accurate VHDL testbenches that read test vectors created from timing diagrams that r epresent transactions. This might be something else you would be intereste d in since you working with VHDL.
If anyone is interested in following the work being done or contributing to new feature ideas, join the google group.
Regards, Dan
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dfab1954

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