Latest threads in Field-Programmable Gate Arrays

Coding style of verilog for FPGA synthesis

hi, guys We design a hardware written in Verilog and synthesize by Synopsys Design Vision. The post-synthesis simulatio...

5 19yrs

lphplab

5 19yrs lphplab

Confused about FPGA devices recommended by Xilinx for my FFT project

Hi everyone. I have selected spartan 3E family for an FFT project due to its low cost. The FFT core (v 4.0) specs say t...

2 19yrs

elet.mirror

2 19yrs elet.mirror

VGA 1080x1920 pixel chipset

Hi, I need a VGA 1080x1920 chip supporting HDTV. Anyone here has used before such IC ? thank you, Vasile

2 19yrs

piclist9

2 19yrs piclist9

Can Cyclone II PLL_out be driven by the pll output c0 and c1?

As I know among the three outputs of pll(c0, c1, c2) only c2 can drive th dedicated PLL_OUT pin, but when in a design,...

5 19yrs

dechenxu

5 19yrs dechenxu

How to deal with RAM issue when generating blif

Hi, I am trying to generate a blif from verilog by using the command, quartus_map; however, there are some issues with...

0 19yrs

wangtiffany313

0 19yrs wangtiffany313

Xilinx FPGA: "after 10ns" constraint

I have some hard to debug issues in my FPGA image processing project: when I read the memory from the Virtex 4 chip at...

9 19yrs

maricic

9 19yrs maricic

Interfacing expansion ports thru EDK

Hello everybody, I am trying interface to the J5 expansion port of the Digilent XUP2VP board through EDK. I read a prev...

0 19yrs

koustav79

0 19yrs koustav79

Trouble using DCMs in EDK 8.2

I'm currently developing a design for the XUP development board. The development software is Xilinx EDk 8.2 The system...

4 19yrs

sego

4 19yrs sego

Intermittent failures seen when bringing a clock into V4LX160 through IBUF to DCM

I'm currently working on a design where there isn't an available GC pin to bring a clock in (bad design, not mine). It'...

1 19yrs

bwilson79

1 19yrs bwilson79

How to choose FPGA for a huge computation?

I have post an topic serveral days ago, and there is the link. http://groups.google.com/group/comp.arch.fpga/browse_thr...

12 19yrs

hitsx

12 19yrs hitsx

Control Panel application for Altera Cyclone II Starter Kit, help?

I'm using Altera's "Cyclone II Starter Kit", and while the board seems to work fine, I can't figure out one of the bund...

2 19yrs

noal

2 19yrs noal

Desperate to find the right FPGA board

Hi guys. First post to this newsgroup, let's pop the champagne ;) I need your advice on selecting a FPGA module for my...

3 19yrs

lists

3 19yrs lists

Multidimensional Register in Modul Port List

Some of my modules implements a register bank controlled by CPU lines. Inside the module I use register banks, like reg...

7 19yrs

bon

7 19yrs bon

What wrong with the DCM of Virtex4 in my project?

I have built a EDK project to program an opb_pci bridge into a virtex4fx60 FPGA, in this design, a 100MHz clock from a...

2 19yrs

lipeng.net

2 19yrs lipeng.net

IBIS Model V5 GTP output

As per my understanding V5 GTP support 1.2V CML standard. I downloaded the V5 IBIS model from Xilinx website but it doe...

5 19yrs

vpatel

5 19yrs vpatel

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