Coding style of verilog for FPGA synthesis

Hello,

It seem to be problem in your test bench (TB). I think you are try to generate stimulus which does not support hardware wrt timing. Timing simulation is the check for timing of your design.

First put timescale directive on the top of TB eg ( `timescale 1ns/

Secondly check your input clock signal frequency in TB. I mean if you are using statement like always #1 clk=~clk in Test bech. It means you are generating 1GHz clock from TB.. be careful. You may also see other input signals like clock in TB.

In short, if you get unknown or high-impedence valuse at th outputs.. it does not mean your design is BAD. First you should check the stimulus. It may wrong..

GOOD LUCK

Regards, Mir

I would get the latest ISE 9.1 and try synthesis using that.

-- Mike Treseler

It could be that you don't have it connected properly in your test bench.

If all of the outputs are unknown, then the inputs are probably unknown too.

Some probing with your simulator should find it. I'd start with clock & reset.

G.

Hi guys,

Thanks for your replies first. I forget to say that function of this design is correct by using Design Vision and the testbench for that and this are the same.

I check description of testbench. Timescale directive was includeded on the top of testbench and the custom design ( `timescale 1ns/10ps).

The clock speed is 5 MHz ( #100 clock = ~ clock) and the design still doesn't work properly.

The input singals are as what I described in the testbench.

I still have no idea about how to debug or modify the design?

Thanks again.

Regards,

Allen

Have you added the clock net to a waveform and actually looked at it? You may have forgotten to initialize the net.

In verilog, ~X === X.

G.