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Can Altera and Xilinx Done signals be tied together? Has anyone done it?

I've got a situation. My software is saying that my two Altera Stratix II FPGAs are successfully programmed, but they don't appear to be. I think something may be erasing them as soon as they're done being configured. I'm programming them in a JTAG chain.

I have the done signals of three FPGAs tied together. Two are the Stratix II and one Xilinx Virtex 4. They're open drain, so they shoulldn't light the Done LED until all three of them are done.

Does anyone see a problem with tying these together?

Reply to
Dale
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Page 14.

'DONE' is itself a bidirectional, active or open drain pin. Thus, the chip is looking at itself (and others tied to DONE).

I suspect that Altera does something similar (yet different) and you are now in a "can't get there from here" mode.

Perhaps there are options in the bitgen software for both vendors that you require (I know we have some options that might help make it work).

Presumably Altera will reply with where their documentation on the subject is located.

Austin

Reply to
austin

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