EDK 9.1.02i warnings flood

Hi!

I recently installed EDK 9,1.02i. When I synthesize a project I get thousand of warnings, which is really annoying:

WARNING: vhdl is not supported as a language. Using usenglish.

Reading the real information becomes almost impossible. What can I do to circumvent this?

Thanks! Matthias

Reply to
charon
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this is hilarious - is your mother tonque really VHDL ? it looks like ISE wants you to use US English instead of VHDL? maybe you speak oxford english, and that upsets it..

sorry, no idea whats wrong, but its just another example of how xilinx understand "software testing..." (lets leave it to our customers...)

Antti

Reply to
Antti

Well, my mother tongue is "de_DE.UTF-8@euro", at least this is what $LANGUAGE is set to. I get warnings in all Xilinx tools because of that. The problem is that the EDK generates a Makefile that sets LANGUAGE to vhdl. The other tools seem to rely on this. When I modify it and set the LANGUAGE to an empty string I don't get these warnings anymore. When I do not touch LANGUAGE I get thousands of warnings with de_DE.UTF-8@euro not supported. BTW the Makefile says it is generated each time so it makes no sense to edit it. So this really isn't a solution. Even if I would set my $LANGUAGE to usenglish the Makefile would override it with vhdl..... If the language in the project preferences is set to verilog it is the same. Arfff...

Matthias

Reply to
charon

I've experienced the same problem on my lab machine running Debian Linux 2.6.15 and EDK 9.1.02i. When I ssh into another lab machine running 2.6.18 Linux, the number of usenglish warnings is reduced to normal. Could be that some other settings on that machine affect how EDK runs, though. Hopefully that might help in some way.

----JD----

Reply to
JD Newcomb

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