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Odelay usage in virtex5

I would like to use Odelay primitive to delay a signal generated in the virtex5 fpga fabric. For this I am hoping to use IODELAY as shown below.

mlinit_in_l is the signal I would like to delay it in 75 ps resolution using odelay as it goes out to the fpga.

mlinit_l is supposed to be the delayed signal but the output stays low. Thus it is not working.

I would like to know how I tell the IODELAY primitive about using it as ODELAY and specify 75 ps resolution?

The user's guide does not seem to have a lot of inofrmation about this.

module linit_delay(mlinit_in_l, mlinit_l);

input mlinit_in_l; output mlinit_l;

IODELAY linit_dly1(.DATAOUT(mlinit_l), .C(1'b0), .CE(1'b0), .DATAIN(mlinit_in_l), .IDATAIN(mlinit_l), .INC(1'b0), .ODATAIN (mlinit_in_l), .RST(1'b0), .T(1'b0) ); endmodule

Reply to
Han Phan
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I don't see what parameters you are using when you instantiate the primitive. Those are very important. And also:

If the V5 ODELAY is anything like the V4 IDELAY (which it probably is pretty close to), the 75ps resolution is NOT GUARANTEED on a per-tap basis. Basically, the delay over all the taps is fixed at some number. For the V4 IDELAY that value is 5ns (200 MHz ref clock period). Dividing that by 64 (number of taps) gives you 78.125 ps per tap.

There is an equation to use for the V4 IDELAY that takes into account the variable nature of the individual tap delays. You'd be suprised at how much +/- there is in each tap. There is a document that describes this in detail. It is XAPP707. I do NOT know if there is a similar document for the V5 IDELAY/ODELAY. It may be that the V5 components don't behave like the V4. I just don't know. There is an equation in the V5 Switching Characteristics Guide, but it may not give the most accurate answers.

But if they are similar to the V4 primitives, then you can't just use one tap and be assured that you are getting an exact delay. You can always check it on a scope and verify it fits your design. Then you are fine...at least for that particular part.

Reply to
motty

Do I need to use the IDELAYCTRL primitive? Currently I have instantiated the IODELAY primitive only to be used as output delay type. Just using the IODELAY primitive, I am able to do the functional simulation.

But I have a confusion about using the IDELAYCTRL primitive. Is this needed for ODELAY? Or is this only for IDELAY?

I have updated the verilog code based on your input as shown but I am not sure what to do with the IDELAYCTRL primitive

module linit_delay(mlinit_in_l, mlinit_l);

input mlinit_in_l; output mlinit_l;

IODELAY # ( .DELAY_SRC("O"), .IDELAY_TYPE("FIXED"), .IDELAY_VALUE(0), .ODELAY_VALUE(2), .REFCLK_FREQUENCY(200.0) )

linit_dly1 (.DATAOUT(mlinit_l), .C(1'b0), .CE(1'b0), .DATAIN(1'b0), .IDATAIN(1'b0), .INC(1'b0), .ODATAIN(mlinit_in_l), .RST(1'b0), .T(1'b0) ); endmodule

Reply to
Han Phan

Yeah, you'll need the IDELAYCTRL. Page 311 of the V5 user guide.

Reply to
motty

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