Field-Programmable Gate Arrays

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ZAP : An open source ARM processor (feedback)

Hi, I am the author of the Gihub project ZAP ( https://github.com/krevanth/ZAP ). It is a 10-stage pipelined ARMv4T com...
15 comments posted 9yrs
posted by revanth91kamaraj
15 comments posted 9yrs posted by revanth91kamaraj

fpga zigbee interface

i have spartan6 atlys(LX45) board, can anyone suggest me how to interface zigbee to this board to communicate with pc.th...
2 comments posted 9yrs
posted by srirameee09
2 comments posted 9yrs posted by srirameee09

Spartan 6 Digital controlled oscillator

Hello, What is the best way to implement a 30 MHz clock generation circuit that can be dynamically controlled to provid...
2 comments posted 9yrs
posted by jontravel24816
2 comments posted 9yrs posted by jontravel24816

Test Driven Design?

Anyone doing any test driven design for FPGA work? I've gone over to doing it almost universally for C++ development, b...
47 comments posted 9yrs
posted by tim
47 comments posted 9yrs posted by tim

Configuration fault recovery

Hi all, I've been thinking about this problem for a while and shared it with a few colleagues, but no one has yet to co...
4 comments posted 9yrs
posted by yan.lamarre
4 comments posted 9yrs posted by yan.lamarre

Pipelining on Multiple Clock Edges

I recall a processor implementation where the guy tried to say that one particular part of the pipeline design had a re...
8 comments posted 9yrs
posted by gnuarm
8 comments posted 9yrs posted by gnuarm

size lattice iCE40 config files

Hi all, I am working on a STM32-based programmer for the olimex iCE40HX1K-EVB fpga dev.board. (now trying to implement...
2 comments posted 9yrs
posted by kristoff
2 comments posted 9yrs posted by kristoff

increment or decrement one of 16, 16-bit registers

I've been geeking out on the COSMAC 1802 lately -- it was the first processor that I owned all just for me, and that I...
22 comments posted 9yrs
posted by seemywebsite
22 comments posted 9yrs posted by seemywebsite

Lattice iCE40 UltraLite DIPSY - what happened?

I was digging around for info on the iCE40 UL and found info on the DIPSY from 2015 when it was breaking news. Not sure...
6 comments posted 9yrs
posted by gnuarm
6 comments posted 9yrs posted by gnuarm

When I'm Wrong I'd Like to Know

But each topic I'm wrong about should be addressed in that newsgroup. If I were wrong about something related to FPGAs...
1 comments posted 9yrs
posted by gnuarm
1 comments posted 9yrs posted by gnuarm

POLL: Would you want to know?

I have said previously I would not post in this group about Jesus any longer. But I fear I have sinned against God in m...
8 comments posted 9yrs
posted by rick.c.hodgin
8 comments posted 9yrs posted by rick.c.hodgin

creating a seed on a FPGA.

Hi, I am aware that the best way to create a seed (for random numbers) is external hardware, but does anybody know any c...
6 comments posted 9yrs
posted by kristoff
6 comments posted 9yrs posted by kristoff

Lattice ECP5 succesor ( with DDR4 phy) ?

AFAIK ECP5 is good for interfacing with DDR3, but not DDR4. Is there a plan to introduce new members with DDR4 or perhap...
4 comments posted 9yrs
posted by brankob
4 comments posted 9yrs posted by brankob

RISC-V Support in FPGA

I don't recall where, but there was a conversation recently about using the RISC-V in FPGAs. Thought I'd pass on the li...
62 comments posted 9yrs
posted by gnuarm
62 comments posted 9yrs posted by gnuarm