RISC-V Support in FPGA

I don't recall where, but there was a conversation recently about using
the RISC-V in FPGAs. Thought I'd pass on the link.
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Rick C
Reply to
rickman
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Ooh, cool. I'm going to have to keep my eye on the RISC-V.
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Tim Wescott 
Control systems, embedded software and circuit design 
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Reply to
Tim Wescott
I don't know how small the RISC-V can be made. I know there is a version designed in an ASIC that can compete with the ARM CPUs and there are more than one version for FPGAs. I would hope they had a version similar to the ARM CM-1 which is specifically targeted to programmable logic and not overly large. I haven't seen any indication this exists, but it is hard to find this type of info. Or I'm just not looking in the right places.
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Rick C
Reply to
rickman
They claim to have a minimal variant of the instruction set, which would presumably be an FPGA-ish sort of thing. But I only read about 20 pages into the instruction set document.
It's OPEN SOURCE! You could get cracking and make one!! (Well, so could I, theoretically, if I were insane).
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Tim Wescott 
Wescott Design Services 
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Reply to
Tim Wescott
Googling RISC-V FPGA implementation got lots of hits.
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Tim Wescott 
Wescott Design Services 
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Reply to
Tim Wescott
Too many, with all that I checked having little value. I've never understood why people go to all the trouble of designing modules and making them publicly available without significant documentation that explains what was done and why. In some 10 or 12 links I was not able to find a single overview of what the project is about, where it is currently and where it is headed.
Whatever. I don't have a strong interest in it at the moment. I have some ideas of my own I want to pursue which is also back burner.
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Rick C
Reply to
rickman
I found reference to there being as many as three variants implemented in FPGAs, but I don't think any are intended for use in FPGAs. Rather I believe these are just test designs along the road to the ASIC which would seem to be out and available on a board for not too much money.
If I wrote one it would be a very simple implementation which would likely require lots of clock cycles to complete anything. But then maybe my impression of the design is not very accurate. I picture it as something very much more complex than the simple and fast stack processors I am used to working with.
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Rick C
Reply to
rickman
A basic RV32I (the minimal 32 bit user-mode instruction set) is very simple. Here's one that's about 400 lines of SystemVerilog, that was designed by a student over a few weeks as a summer project:
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Theo
Reply to
Theo Markettos
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is the manifesto.
Theo
Reply to
Theo Markettos
I would at least hope that the result would be on the level of gate usage as a Cortex M1.
OTOH, since Day 1, the RISC architecture has been about getting the most bang for your logic buck -- and you can always leave out the bells and whistles like branch prediction and pipelines and whatnot.
If they did their job right, you'll find that much of the "logic" can be coded as static wires -- that's why they do things like always have information fields (like register addresses, or immediate data) appearing in the same spots.
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Tim Wescott 
Wescott Design Services 
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Reply to
Tim Wescott
That's typical of open-source projects: functionality is fun; good documentation is at least as time-consuming as good code (HDL or software), and documentation-writing isn't nearly as fun.
For cutting-edge open-source stuff the key to success is to find the web forum or mailing list that covers the subject, and to start asking questions. I suppose that if I won the lottery and didn't get seduced by Tahiti I'd pick a project and just write documentation.
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Tim Wescott 
Wescott Design Services 
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Reply to
Tim Wescott
Or you find a company (ideally run by at least some of the people behind the open source project) that will provide you with support, documentation, demos, point-and-click installations (especially for Windows), etc. - all for a bit of money. When it works well, it can give you all the benefits of a good open source project, /and/ all the benefits of a good commercial project, for a price somewhere in between.
I don't know if there is such commercial support available for RISC-V - but if it gets popular enough, then I am sure there will be.
Reply to
David Brown
An older version of the Risc V processor generator is here:
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This is the 1 stage version:
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A more recent version by the same group seems to be this BOOM Risc V which is synthesizable.
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This presentation seems to cover all versions:
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The CPU is implemented in Chisel which is a scala library that compiles to Verilog or C++.
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Reply to
Emilian Miron
Tim, all,
(...)
F.Y.I. One of the main mailing-lists is here: snipped-for-privacy@groups.riscv.org
Traffic is relative low (about 15 messages a week), so quite easy to follow without getting flooded in messages.
more info:
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Kristoff
Reply to
kristoff
For those who are confused, RISC-V is not a *processor*, it's an *architecture*.
Anyone can come up with a microarchitectural implementation of the architecture - that's the point of an open source ISA. Being open-source you can also change the architecture - but it's then your problem to maintain the OS/compiler/etc for your fork of the architecture.
Berkeley happen to have some of their own implementations that they have also open sourced. These might or might not suit your purposes. Being in Chisel is one thing that's not everyone's cup of tea.
But the idea is that everyone has an architectural licence, so they are free to come up with their own implementations, and share them. I suspect that Microsemi have done their own, rather than importing the Berkeley cores, for instance.
(That RISC-V bears a certain resemblance to MIPS is not entirely accidental; MIPS has long been used as a simple ISA for teaching, which is one role that RISC-V fills without treading on any toes [patents] of Imagination Technologies)
Theo
Reply to
Theo Markettos
Thanks for the link, this is useful to learn about the instruction set. Not much info on the available implementations.
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Rick C
Reply to
rickman
I see a total lack of documentation on amateur projects where someone designs something and tosses it up on one of the source sharing sites. But a major project like this is about being used. I don't think this is just a few guys who thought it would be cool to design a chip. This chip has been built as an ASIC and has multiple incarnations for FPGA. It would tremendously help encourage implementations to have a decent description of what is available.
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Rick C
Reply to
rickman
Pretty small (and fast):
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Reply to
Robert F. Jarnot
I suppose this is one reason that Octave works so well for me: when I have a question, I consult the Matlab documentation. That makes feel a little guilty. I've found Octave is actually faster on a lot of my scripts though .
Sadly, when you mentioned Tahiti, I was trying to figure out if that was th e name of some obscure HDL or open-source project. It took me a minute to figure out you meant the place where Gaugin hung out. Yeah, that might be better than writing documentation.
Reply to
Kevin Neilson
The code looks pretty clear at first glance. I see a lot of SystemVerilog constructs that don't look synthesizer-friendly, though.
Reply to
Kevin Neilson

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