Field-Programmable Gate Arrays

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Cyclotomic FFTs

I've been researching cyclotomic FFTs. There is a lot of literature (Fedor enko, Trifinov, Costa, etc.) about using thi...
0 comments posted 9yrs
posted by kevin.neilson
0 comments posted 9yrs posted by kevin.neilson

glitching AND gate

I have a question about how FPGAs handle signals into combinational logic. I have following setup: always @(posedge inte...
25 comments posted 9yrs
posted by dab
25 comments posted 9yrs posted by dab

versatile_FFT core has no output

I am trying to use https://github.com/freecores/versatile_fft , but after I run "make all", data_out.txt and res.txt are...
1 comments posted 9yrs
posted by feiphung27
1 comments posted 9yrs posted by feiphung27

FPGA as heater

We have a ZYNQ whose predicted timing isn't meeting decent margins. And we don't want a lot of output pin timing variat...
47 comments posted 9yrs
posted by jjlarkin
47 comments posted 9yrs posted by jjlarkin

How to download ISPLSI 1032 and how to program it?

ISPVM 18.1 and ISP (HW-USBN-2A) are connecting and downloading and it says that there is no information of ISPLSI 1032...
0 comments posted 9yrs
posted by marsuan40
0 comments posted 9yrs posted by marsuan40

handshacking between modules, best practices ?

Hi, Last weekend, I was continueing on my small project to use a FPGA as DAC. I now use a hardware DAC (tlc5615). So I...
6 comments posted 9yrs
posted by kristoff
6 comments posted 9yrs posted by kristoff

Simulation of PCIe at TLP level

Hi, has anybody simulated PCIe at TLP level? I would like to feed a 1x PCIe endpoint interface with data as if it was i...
1 comments posted 9yrs
posted by svenn.bjerkem
1 comments posted 9yrs posted by svenn.bjerkem

The Lord calls out to you for repentance, salvation

The message is simple: He wants to forgive your sin and give you eternal life in the paradise of God. If you have sin,...
1 comments posted 9yrs
posted by rick.c.hodgin
1 comments posted 9yrs posted by rick.c.hodgin

Analog to digital converters

I don't know where to ask this, so I'll try here. Are analog to digital converters fundamentally, in their core inner d...
10 comments posted 9yrs
posted by rick.c.hodgin
10 comments posted 9yrs posted by rick.c.hodgin

Go to church on Sunday

The Creator of the universe calls you to be with Him where He is in the paradise of Heaven. He wants to forgive your si...
6 comments posted 9yrs
posted by rick.c.hodgin
6 comments posted 9yrs posted by rick.c.hodgin

temperature sense diodes in Xilinx 7 series

Has anybody used these? We have two FPGAs on a board, a Zynq and an Artix7. We want to use the internal ADCs to read ch...
6 comments posted 9yrs
posted by jjlarkinxyxy
6 comments posted 9yrs posted by jjlarkinxyxy

Master Xilinx FPGA like Jtag bridge.

How to make master FPGA to connect to many FPGAs ? Two FPGAs connected by serial TDI - TDO, and two fpgas TMS TCK TDO a...
10 comments posted 9yrs
posted by abirov
10 comments posted 9yrs posted by abirov

designing a fpga

Hi all, A couple of weeks ago, I was watching the talk of Wolf Clifford on his opensource fpga flow at ccc. (https://ww...
38 comments posted 9yrs
posted by kristoff
38 comments posted 9yrs posted by kristoff