Field-Programmable Gate Arrays

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Using PlanAhead for Partial Reconfiguration

I have a doc. named "Partial Reconfiguration Design with PlanAhead 9.2" and use PR_V5_DVI.zip for example. While follow...
1 comments posted 19yrs
posted by gilbert1219com
1 comments posted 19yrs posted by gilbert1219com

how interfacing of cpld and cpu done?

please give me information about inerfacing of cpld xc9572 & cpu
1 comments posted 19yrs
posted by nanaware_amit
1 comments posted 19yrs posted by nanaware_amit

hardware software codesign

Hi there I am a newbie to FPGA based development. So I have a Xilinx II board. What I need to do is basically implement...
2 comments posted 19yrs
posted by gks.1981
2 comments posted 19yrs posted by gks.1981

Comparing Adder synthesis techniques

Hi, I am working on a study to copmpre the effiency of synthesied adders. I have built a ripple adder and a carry look...
3 comments posted 19yrs
posted by jozamm
3 comments posted 19yrs posted by jozamm

DMA scatter gather with PLB bus?

Hi everyone. I'm trying to transfer data from DDR memory to a custom PLB_IPIF peripheral in a Virtex II Pro XUP card. I...
2 comments posted 19yrs
posted by cesar.pedraza
2 comments posted 19yrs posted by cesar.pedraza

proasic plus. actel

thanks Thomas Stanka! But... In my code I have instantiated a GL Buffer (is a fast clock). But in the synthesis: the lo...
1 comments posted 19yrs
posted by dorama2
1 comments posted 19yrs posted by dorama2

Multi-cycle paths in VHDL libraries

Hi everyone, may I ask you a question. I'm trying to find out how to handle multi-cycle paths in VHDL libraries. I'm us...
0 comments posted 19yrs
posted by knittel
0 comments posted 19yrs posted by knittel

Gated Clock Problems

Hi everyone, I am running into a really peculiar problem for a research project that I am working on. The circuit is fa...
29 comments posted 19yrs
posted by dont
29 comments posted 19yrs posted by dont

help! ACTEL PROASIC PLUS clock buffer

Hi!, I have a big problem: I use Libero to Proasic Plus Family of Actel. My FPGA has got 4 global pin (4 GL macro), I n...
7 comments posted 19yrs
posted by dorama2
7 comments posted 19yrs posted by dorama2

FPGA history

Hi all, for my PhD thesis I am looking for a citeable publication describing the FPGA technology advances during the re...
5 comments posted 19yrs
posted by sven.heithecker
5 comments posted 19yrs posted by sven.heithecker

Population Count circuit

Out of curiosity: I am currently studying some problems which require many population- count operations ov various size...
8 comments posted 19yrs
posted by acd4usenet
8 comments posted 19yrs posted by acd4usenet

Looking for fast AES cores with low latency

Hi, Since the initial rash of AES / Rijndael cores a few years ago, I haven't seen much research at the high speed end....
10 comments posted 19yrs
posted by allanherriman
10 comments posted 19yrs posted by allanherriman

Data-side BRAM

Hello All, there is a 32bit Data Bram. I am trying to load a 32 bits data in the fourth location (4) of the Bram (0-255...
0 comments posted 19yrs
posted by lastval
0 comments posted 19yrs posted by lastval