Okay .... the RS-232 is a serial interface with a uart block dealing with the parallel (byte wide tx/rx) to serial data conversion.
Take a look at the Xilinx coregen generator or opencores.org for uart source code. I will paste some of one of my own designs at bottom.
The nice thing about using the RS-232 UART approach is that with a three wire cable (GND, TX, RX) you can connect to a serial port on a PC, open the windows utility hyperterm, and be able to debug your interface. A starting point might be to wrap the rx serial data to tx serial data (skip the usarts ... your just wrapping the tx and rx) and make sure every character you type is received by hyperterm. Then you can add the tx and rx usarts ... and verify the same level of functionality.
If you are a newbie, make sure you get a copy of a simulator (Modelsim) for debugging your FPGA code. There is an upfront investment in learning this tool, but the payback is huge. Same thing for something like chipscope, the Xilinx logic analyzer like function.
--------------------------------------------------------------------- for the tx_uart the clk was approx 20 Mhz (19.91) for the rx_uart the sys_clk_100mhz was really 100 mhz. you will need to defparam (overide) at one level up where these are instantiated, or if you want to change within module that is fine also. Change these values to align with your clk rate, and desired baud rate.
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module tx_uart ( sys_clk_100mhz, cr_rst, tx_data_ld, tx_data_byte, tx_byte_done, tx_ser_dat_out );
input sys_clk_100mhz; input cr_rst; input tx_data_ld; input [7:0] tx_data_byte; output tx_byte_done; output tx_ser_dat_out;
parameter TC_19200_VALUE_52p08_us = 14'h040C; // parameter TC_19200_VALUE_52p08_us = 14'h015B; // TC_57600_VALUE_17p36_us // parameter TC_115200_VALUE_8p68_us = 14'h00AD; // TC_115200_VALUE_8p68_us
reg baud_19200_event, pending_tx_ld, tx_byte_done; reg [3:0] txbyte_bit_ctr; reg [7:0] txbyte_hold_reg; reg [13:0] baud_19200_rate_ctr; reg [10:0] sdo_shift_reg;
wire baud_19200_rate_ctr_tc = (baud_19200_rate_ctr == 14'h0000); wire odd_parity = ^~(txbyte_hold_reg[7:0]); wire sdo_shift_reg_ld = pending_tx_ld & baud_19200_event; assign tx_ser_dat_out = sdo_shift_reg[0];
always @ (posedge sys_clk_100mhz) begin baud_19200_event