Has anyone got any example Verilog code for this? I'm currently using Quartus wizard generated code and wrapping it up in a Verilog module so I can use my own parameters instead of running the wizard each time I need a new variation (which is a complete pain). I thought that perhaps inferring the memory might yield better and more efficient results.
Ta.
I have such a piece of code but it only works for Xilinx parts. (Which you should use.) Most likely the synthesizer will not infer RAMs of different port widths from a behavioral description. My code takes Verilog parameters that are passed in and then uses 'generates' to instantiate an array of the correct blockRAM primitives with the primitive parameters set for asymmetric port widths if necessary. You'll probably need to do something similar if you want an HDL solution. I'm not sure why the tools don't support this yet. A behavioral description of an asymmetric RAM is slightly awkward, but definitely doable.
-Kevin
Thanks, I haven't tried to infer because I wasn't sure how to tackle the Verilog for differing port widths. It can be done easily with the wizard, but this is cumbersome when it comes to writing a neat re-usable unit. Dave.
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