For example, I have two wires FA[23:1] (address line for Flash) and RAM_A_SD[63:0] (data line for SRAM), due to the number of pins constraint, FA and RAM_A_SD share the same FPGA pins (seen from outside of FPGA). I tried to assign those two wires to the same pins in pin assignment file, but got errors from Xilinx ISE mapping process, saying that it is incorrect to assign two wires to the same pin and cannot resolve the pin assignments. Just wondering whether it is possible to use both Flash and SRAM outside of FPGA in this case, or should I tri-state every single data line which shares the same pin with other wires, such that there is only one wire goes into a particular pin (seen from inside fpga)? cheers, -Wei
- posted
16 years ago