I am running into a really peculiar problem for a research project that I am working on. The circuit is fairly simple one, which needs to measure which one of two signals reaches a flip-flop first. Two impulses are sent through two different paths, and they are both fed to a D flip-flop. The circuit uses a nifty trick for outputting which signal got there first.
One of the signals (signal A) is connected to the D input, and the other one (signal B) to the Clock input. Both signals get a 0-to-1 transition. If signal A arrives first, D is '1' when there is a transition on Clk, so output of flip-flop is 1:
|------------- A (D) | ____|
|------------- B (Clk) | __________|
If signal B gets there first, then when Clock occurs, D is still '0', so output is '0'
|------------- D | _________|
|------------- Clk | ____|
(I hope my feeble attempts were sufficient to demonstrate the situation)
It was pretty easy to code this using VHDL; I just needed to connect the signals correctly.
The problem is that during the Place & Route phase, I receive a warning telling me that I have a clock signal coming from a combinatorial, gated circuit. As I have pointed out, this is actually what I want. The peculiar problem manifests itself as follows: When I synthesize it, the Device Summary correctly finds 64 slices that are being used. Yet when I run PAR, that number suddenly becomes 8 slices! I think the reduction in the slice count is due to the given warning, since the rest of the circuit behaves as expected.
Can anybody tell me how I should deal with this situation? I have tried using a CLOCK_SIGNAL attribute, but I doubt that's what I want.
I would appreciate any help, Thanks, Berk Birand