Hi
In Cyclone II ep2c5 pinouts document:
DQS signals are assign to this pins because this pins are routed directly to the clock control block and global clock bus.
But why DQx (data) and DM (data mask) signals are assign to this pins.
Is that requisite assignment or only recommended? If recommended then why?
This assignment is not comfortable for me but I don't know whether I can change it.
Thanks for any information.