Altera devices connecting to DDR memory.

Hi

In Cyclone II ep2c5 pinouts document:

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Some pins have additional discription: DQxxx DQSxx DMxx.

DQS signals are assign to this pins because this pins are routed directly to the clock control block and global clock bus.

But why DQx (data) and DM (data mask) signals are assign to this pins.

Is that requisite assignment or only recommended? If recommended then why?

This assignment is not comfortable for me but I don't know whether I can change it.

Thanks for any information.

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PGW
Reply to
pgw
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Hi,

memory interface section"), DQS assignments are required while DM assignments are only recommended. I think that it allows you to use some dedicated circuitry that helps to meet the tight DDR timing requirements.

BTW, do you understand well how each line should be terminated (SSTL-2 signaling) ? I have problems with this. If you are pretty sure of your electrical schematics, could you send them to sebastien dot bourdeauducq at gmail dot com ?

And what are the on-chip termination series resistors ? 25 ohm or 50 ohm ?

Regards,

Sebastien

Reply to
Sebastien Bourdeauducq

Thanks for this information.

I think it should be 25 because 50 is to mach. But I don't use on-chip termination only external resistors because "Optimal value ... should be determined by simulations." this quotation is from:

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(Many helpful informations in this AN)

Secound reasone: "When using on-chip series termination, programmable drive strength is not available." Cyclone II Handbook. This AN is also interesting:

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PGW
Reply to
pgw

I forgot. Some schematics you can find in Altera kits documentations

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Cyclone II Starter Development Kit Cyclone III Starter FPGA Kit Nios II Development Kit, Cyclone II Edition (2C35)

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pgw
Reply to
pgw

document:

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Typically, each 8 bits of DQ and corresponding DM bit are grouped together with an associated DQS bit. The idea is that individual pins in this group will see similar skews. Therefore, the DQS to data/dm relationship will not suffer at the memory or fpga. If you are going to be running at the max rated operating frequency it would be important to keep the group as suggested.

-sanjay

Reply to
parekh.sh

Thanks for response.

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pgw
Reply to
pgw

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