Altera devices connecting to DDR memory.

Hi,

memory interface section"), DQS assignments are required while DM assignments are only recommended. I think that it allows you to use some dedicated circuitry that helps to meet the tight DDR timing requirements.

BTW, do you understand well how each line should be terminated (SSTL-2 signaling) ? I have problems with this. If you are pretty sure of your electrical schematics, could you send them to sebastien dot bourdeauducq at gmail dot com ?

And what are the on-chip termination series resistors ? 25 ohm or 50 ohm ?

Regards,

Sebastien

Thanks for this information.

I think it should be 25 because 50 is to mach. But I don't use on-chip termination only external resistors because "Optimal value ... should be determined by simulations." this quotation is from:

Secound reasone: "When using on-chip series termination, programmable drive strength is not available." Cyclone II Handbook. This AN is also interesting:

I forgot. Some schematics you can find in Altera kits documentations

Cyclone II Starter Development Kit Cyclone III Starter FPGA Kit Nios II Development Kit, Cyclone II Edition (2C35)

document:

Typically, each 8 bits of DQ and corresponding DM bit are grouped together with an associated DQS bit. The idea is that individual pins in this group will see similar skews. Therefore, the DQS to data/dm relationship will not suffer at the memory or fpga. If you are going to be running at the max rated operating frequency it would be important to keep the group as suggested.

-sanjay

Thanks for response.