Field-Programmable Gate Arrays

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where to download latest systemc libararies?

where to download latest systemc libraries? i checked www.systemc.org, but there is no link for download.
1 comments posted 18yrs
posted by e2point
1 comments posted 18yrs posted by e2point

MIG for Linux?

So I thought I would try out this MIG thing I see mentioned occasionally, But according to http://www.xilinx.com/xlnx/x...
7 comments posted 18yrs
posted by junkmail
7 comments posted 18yrs posted by junkmail

Newbie,the simplest way to program an FPGA at home?

Hi i 'm trying to practice VHDL at home,until today i did some things using obsolete Lattice and Xilinx CPLD. One year...
7 comments posted 18yrs
posted by bliscachiocciolinatiscali.it
7 comments posted 18yrs posted by bliscachiocciolinatiscali.it

NgdBuild:455 Multiple Drivers

I'm working with XILINX ise 9.2i; designing a deserializer & using 2 DCM's in sequence to generate 4 100MHz clocks (eac...
1 comments posted 18yrs
posted by lzkelley
1 comments posted 18yrs posted by lzkelley

Graphical VHDL Viewer ?

Hi all, Does anyone know a free/simple software that would use vhdl files to produce a graphical view ? The goal is to...
9 comments posted 18yrs
posted by sjulhes
9 comments posted 18yrs posted by sjulhes

Xilinx OCM memory use limitations ?

Hi all, We are building a very simple SOC ( PPC 405, internal memory, UART light) in a V4FX60, with a very simple firmw...
2 comments posted 18yrs
posted by sjulhes
2 comments posted 18yrs posted by sjulhes

Quartus II 7.2 web edition - Linux or not?

I just got an email from Altera, saying: ear Altera Customer, The new Quartus® II Web Edition Software version 7.2 is n...
12 comments posted 18yrs
posted by hpa
12 comments posted 18yrs posted by hpa

Re: UK Supplier XILINX spartan 3 development board??

>>Hi Dan, >>What's wrong with US products? >> >>Those yanks have invented a thing called FedEx. Perhaps you've heard of...
2 comments posted 18yrs
posted by symon_brewer
2 comments posted 18yrs posted by symon_brewer

Xiinx ERROR:PhysDesignRules:10

Hi all, I've got a design that can be built in 2 different configurations, controlled via a VHDL constant / if-generate...
1 comments posted 18yrs
posted by markm
1 comments posted 18yrs posted by markm

FPGA tools under VMware or Parallels on a Mac?

Which vendor's FPGA development and USB download tools have people found to work reliably on a Mac or MacBook under eit...
5 comments posted 18yrs
posted by rhnlogic
5 comments posted 18yrs posted by rhnlogic

Cyclone II SSTL-2 on-chip resistors

Hi, I'm trying to build a board that will use a DDRAM PC2700 memory module connected to a Cyclone II FPGA. It uses SSTL...
2 comments posted 18yrs
posted by sebastien.bourdeauducq
2 comments posted 18yrs posted by sebastien.bourdeauducq

HELP, how to time constraint part of a design?

Hello Could someone tell me how to make timing constraints in a particular part of a VHDL design? Inside my design I ha...
13 comments posted 18yrs
posted by DoVHDL
13 comments posted 18yrs posted by DoVHDL

What happened to Confluence and HDCaml?

It seems that the launchbird site has disappeared. I had heard that Confluence was superceded by HDCaml, but it looks l...
4 comments posted 18yrs
posted by rubyfan
4 comments posted 18yrs posted by rubyfan