Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15253 Threads Posts
to

Spartan-3E display developpement kit

Hello, I 'm trying to use the Spartan-3E display developpement kit. I can program the FPGA with JTAG ( file.bit in dire...
0 comments posted 18yrs
posted by bhb22l
0 comments posted 18yrs posted by bhb22l

Re: Ping Jim: The PFD is dead!

>> >>Finally, proof positive! The PFD fails to detect phase! I'm sure you will be >>happy to know this important inform...
8 comments posted 18yrs
posted by jjlarkin
8 comments posted 18yrs posted by jjlarkin

Capability of a FPGA device.

Hi, For a future project we are considering the use of FPGA technology and IP cores instead of using an ASSP solution....
7 comments posted 18yrs
posted by Spam
7 comments posted 18yrs posted by Spam

xilinx bmm file problem

hello, Has anybody experience with xilinx bitfile merging using a bmm file? I've a small processor core running in a sp...
3 comments posted 18yrs
posted by tralalal
3 comments posted 18yrs posted by tralalal

Is it possible to debug a vhdl design over jtag?

Hi, I would like to debug a vhdl design over Jtag. Is it possible?. As XMD for EDK but for vhdl code. My best regards Pa...
7 comments posted 18yrs
posted by pbantunez
7 comments posted 18yrs posted by pbantunez

Weird behavior : Altera DE2, C++, For loops, SRAM

So I've implemented a NIOS II board using the SOPC builder. I ran out of on-chip memory so I went off-chip to the DE2's...
1 comments posted 18yrs
posted by sendthis
1 comments posted 18yrs posted by sendthis

debugging ppc + mb

Hi all, I would like to debug a system containing a microblze and a ppc405. I'm using the xmd (gdb) for both of these u...
4 comments posted 18yrs
posted by me_2003
4 comments posted 18yrs posted by me_2003

Updating my bookshelf

Hello all I am looking for references of books about digital design (ASIC & FPGA, high speed, processor, signal process...
4 comments posted 18yrs
posted by nic_o_mat
4 comments posted 18yrs posted by nic_o_mat

IDE to Flash memory

Hi, I'm looking for some ideas to make an IDE to NAND or NOR flash memory interface. Have you ever heard about something...
4 comments posted 18yrs
posted by franck.jullien
4 comments posted 18yrs posted by franck.jullien

Free & open source USB STAPL Player

Hi All, I have just released a free & open source USB STAPL Player - a small device which may control multiple JTAG cha...
0 comments posted 18yrs
posted by wzab
0 comments posted 18yrs posted by wzab

Xilinx, MIG, UCF: timing constraints for DDR2 DRAM

Hi FPGA Group! I'm struggling to get a fast speed (~ 200 MHz) for the DDR2 DRAM interface, generated with the Xilinx Me...
3 comments posted 18yrs
posted by sheinzle
3 comments posted 18yrs posted by sheinzle