can i use dual edge or two clocks?

My FPGA master clock is at 100MHz. I have assigned a counter to count from 0 to 99 to achieve a period of 1usec. As the counter is counting from 0 to 99, i will take 1 sample at each count and therefore i have a total of 100 samples. Now my task requires me to increase my sample size to 200. However, i can't increase the counter count to 0 - 200 as this will increase the period to 2usec. My task requires me to double the sample size while maintaing the period at 1usec.

I tried to implement this by adding another clock to the system but i am not able to synthesis the code as one clock is only allowed same for dual edge behavior of the clock pulse. I am running out of ideas how to accomplish this task as i am not very strong in VHDL coding and my deadline is nearing. Would appreciate if someone can help me. Thanks!!

Reply to
raullim7
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Use a PLL to double the clock frequency, if your FPGA has one.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

Or a DDR input cell (assuming your FPGA has them), or even two flipflops, one positive-edge triggered and one negative. Of course, this assumes your 100MHz clock is of good enough quality, ie closely symmetric.

Reply to
David R Brooks

snipped-for-privacy@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de

Hi Frank, i am not allowed to double the clock frequency, my clock period have to remains at 10ns(1usec/100).

Reply to
raullim7

Have half of the samples sampled with the pos edge of the clock and the other half caught with the neg edge of the clock. Treat these as asynchronous clocks.

Mike

Reply to
Mike Lewis

snipped-for-privacy@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de

Reply to
Peter Alfke

Is the requirement to keep the period at 1usec or the frequency at 100Mhz?

mike

Reply to
Mike Lewis

Maybe you misunderstood me: The PLL is inside the FPGA (at least in Spartan, Cyclone etc.). Most FPGA clock circuits even provide multiple outputs. So you can run the rest of your design at 100 MHz and the sampling at 200 MHz. But maybe you need some FIFO and other tricks to couple it to the 100 MHz domain, or if the speed is too high for your built-in memory or external memory.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

Sounds like a homework restriction to me.

---Matthew Hicks

Reply to
Matthew Hicks

Perhaps this is a task for a 5ns delay line then ? The tutor may not have restricted those ;)

-jg

Reply to
Jim Granville

What are you sampling? Where do the samples go?

If you store your samples in some sort of a memory buffer, just add another buffer of the same size and write to it on falling edge.

/Mikhail

Reply to
MM

Hi Jim, I think we may need to be more creative than that. I suggest accelerating the tutor to about 0.866 times the speed of light while carrying out the FPGA sampling. From his point of view, the sampling will then be at ~200MHz. Or maybe give him a barometer? HTH., Syms.

Reply to
Symon

and that gives me another idea -[just in case the tutor was smart enough to say no active components], the OP could use appx 1m of wire as a delay line. He'd need to measure and trim it to whatever precision was needed, but my rusty collection is ~200m/us (after velocity factor correction)

- an "A" student would make a vernier screw sliding contact, allowing fine adjustments of the 5ns delay.

-jg

Reply to
Jim Granville

Hi.. i have the counter which have 100 clock pulses and therefore a period of 1usec. Its an assignment and the requirements state that i cant change the period of the counter. Below is my code which i am not able to compile, stated that COUNTER2 cannot be synthesized, bad synchronous description.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; use ieee.std_logic_arith.conv_std_logic_vector;

entity dualEdge is GENERIC (T_PROP : REAL := 0.0); PORT ( CLK : IN STD_LOGIC; --IN BIT := '0'; RESET : IN BIT := '0'; -- RESET Out1 : OUT BIT := '0'; -- Phase 1 signal Out2 : OUT BIT := '0'; -- Phase 2 signal

end dualEdge;

architecture Behavioral of dualEdge is CONSTANT del : TIME := T_PROP * 1 sec;

begin PROCESS(CLK, RESET)

VARIABLE CLKOUT : STD_LOGIC; VARIABLE ontime : INTEGER RANGE 0 TO 99:= 0;

-- Counters for genrating the pulses VARIABLE COUNTER : INTEGER RANGE 0 TO 2000 := 0; VARIABLE COUNTER1 : INTEGER RANGE 0 TO 99:= 0; VARIABLE COUNTER2 : INTEGER RANGE 0 TO 99:= 0;

BEGIN -- WAIT ON CLK; IF RESET='0' then

-- Counters for generating the delays. COUNTER1 := 0; -- 0 Offset COUNTER2 := 0; -- 0 Offset COUNTER := 0; -- 0 Offset

-- ELSIF (rising_edge(CLK)) THEN

CLKOUT := NOT(CLKOUT);

IF(COUNTER = 0) THEN ontime := 10; END IF;

IF (COUNTER1 >= 99) THEN -- MOD 100 Counter COUNTER1 := 0; ELSE COUNTER1 := COUNTER1 + 1; END IF; -- Generate the Pulse IF (COUNTER1 < ontime) THEN Out1 = 99) THEN -- MOD 100 Counter COUNTER2 := 0; ELSE COUNTER2 := COUNTER2 + 1; END IF; END IF; END PROCESS; end Behavioral;

Basically, everything that i include in the falling_edge loop is unable to synthesize. Kindly point out my errors and advise on the correct way to write it. Thanks a million to every advise.

Reply to
raullim7

On 2 Nov., 05:04, snipped-for-privacy@hotmail.com wrote: [..]

You have two complete independend counters. So you could just split the process in two, having one process with pos edge and one with neg edge.

BTW Why do you usee bit instead of std_logic(_vector) as IO? I wouldn't mix numeric_std and std_logic_arith

bye Thomas

Reply to
Thomas Stanka

hey guys, i managed to get two signals already.. thanks for all the help and advices...

Reply to
raullim7

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