Hi.. i have the counter which have 100 clock pulses and therefore a period of 1usec. Its an assignment and the requirements state that i cant change the period of the counter. Below is my code which i am not able to compile, stated that COUNTER2 cannot be synthesized, bad synchronous description.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; use ieee.std_logic_arith.conv_std_logic_vector;
entity dualEdge is GENERIC (T_PROP : REAL := 0.0); PORT ( CLK : IN STD_LOGIC; --IN BIT := '0'; RESET : IN BIT := '0'; -- RESET Out1 : OUT BIT := '0'; -- Phase 1 signal Out2 : OUT BIT := '0'; -- Phase 2 signal
end dualEdge;
architecture Behavioral of dualEdge is CONSTANT del : TIME := T_PROP * 1 sec;
begin PROCESS(CLK, RESET)
VARIABLE CLKOUT : STD_LOGIC; VARIABLE ontime : INTEGER RANGE 0 TO 99:= 0;
-- Counters for genrating the pulses VARIABLE COUNTER : INTEGER RANGE 0 TO 2000 := 0; VARIABLE COUNTER1 : INTEGER RANGE 0 TO 99:= 0; VARIABLE COUNTER2 : INTEGER RANGE 0 TO 99:= 0;
BEGIN -- WAIT ON CLK; IF RESET='0' then
-- Counters for generating the delays. COUNTER1 := 0; -- 0 Offset COUNTER2 := 0; -- 0 Offset COUNTER := 0; -- 0 Offset
-- ELSIF (rising_edge(CLK)) THEN
CLKOUT := NOT(CLKOUT);
IF(COUNTER = 0) THEN ontime := 10; END IF;
IF (COUNTER1 >= 99) THEN -- MOD 100 Counter COUNTER1 := 0; ELSE COUNTER1 := COUNTER1 + 1; END IF; -- Generate the Pulse IF (COUNTER1 < ontime) THEN Out1 = 99) THEN -- MOD 100 Counter COUNTER2 := 0; ELSE COUNTER2 := COUNTER2 + 1; END IF; END IF; END PROCESS; end Behavioral;
Basically, everything that i include in the falling_edge loop is unable to synthesize. Kindly point out my errors and advise on the correct way to write it. Thanks a million to every advise.