Re: Ping Jim: The PFD is dead!

But the Inventor mentioned the additional jitter due to uncorrelated noise of the 2 PFD outputs and their summation in your example, and the evil glitches due to unmatched symmetry and parasitic coupling of the digital to the analog ! This must be worth a patent.

Having read

i now fear the evil glitch and deadtime jitter to corrupt my computer before global warming blasts icebergs and blazes glaciers.

Oh, the guy is clearly a lunatic, and an amateur lunatic to boot. His writing is hilarious.

But the dual-diode thing solves a couple of problems using an FPGA as a phase-frequency detector.

John

The tristate drive is seen in many PFD's. Tristate works well, but does float the FPGA pin at the Opmap Bias point, and is also a noise-injection point. Also either the Diode, or Tristate directly couple the FPGA Vcc and GND noise into the integrator (when ON)

So the "purists PFD", would use a TinyLogic analog Switch, [example of 2 in one package : 74LVC2G66 ] and keep the Hi-Z integrator node tiny, and shielded from digital charge injection, and power supply noise.

Also, some designs have deliberate overlap in the PFD impulses, as that avoids a dead-band, which can give higher spurious noise spurs.

-jg

The diode thing allows true overlap (ie, zero deadband operation) without worrying about relative pfet/nfet drive strengths or tristate enable times. It also eliminates a more subtle problem related to pin capacitances, which would add yet another nonlinearity to the already nonlinear xapp circuit.

Skyworks makes some 0.22 pF, SC79 schottkies that would be ideal here.

Loop gain doubles in the overlap region, but that's easy to deal with. It's sure better than a flat spot.

The opamp situation can be interesting.

John

Yes, better systems take effort to avoid any dead-band

With the single-resistor drawn in the Xilinx app note, it gets worse

- there is buffer contention during that (short) time = more unknowns

-jg

Guys, Beware of XAPP028...

From

Quote:- A small note of caution when using Peter's XAPP028 in Virtex II. As well as constraining the logic to the CLBs shown in the app note, make sure you specify a MAXSKEW attribute on the reference signal and feedback signal to the circuit. I use 100ps. Without this the circuit can occasionally malfunction depending on the place and route. (These are the signals called 'from VCO divided by N' and 'from reference frequency'.) There was no problem when this circuit was used on older FPGAs where the routing to the F and G lookup tables in a single CLB was guaranteed to have low skew. In Virtex II this is no longer the case and a single signal that goes to both the F and G inputs of a CLB can have significant skew if not constrained. This can cause the circuit of XAPP28 to misbehave.

HTH., Syms.

Thanks, Syms, for pointing this out. I published this in 1990, in the XC3000 era, and I was proud of packing it so nicely. Your comment makes me retire the circuit, but it will unfortunately survive on the internat... Peter