Hi all, I'm experiencing problems with adding custom logic to an IP core that I have generate in EDK. I changed the vhdl file of an auto- generated IP core that is connected via FSL to the FPGA, but the behaviour of the program remains still the same. I've tried also to re- import the modified core to the project, but I still get errors due to the fact that the file xparameters.h doesn't contains the appropriated names. How can I do to let EDK notice changes in vhdl files? Thank you in advance!
Giulio