33+ Regs in PLB IPIF

The wizard generates 2 files, the top file and the user logic file. Make sure that the constants are set up correctly in both files.

Yeah, I made extra sure this was happening. Somehow, I've now got it to read and write up to 64 registers.

---Matthew Hicks

Changing the values of the generics will only set up the proper address decoding for your IP core, however it will not automatically instantiate the required amount of registers.

If you look at the user_logic.vhd file you will see slv_regX declarations for every register where X goes from 0 to N. You will have to modify this code to include the proper amount of registers as well if you want everything to work properly.

Does your IP core need constant access to the values that will be stored in the registers, or could you just throw the values in a BRAM?

-Jas> Yeah, I made extra sure this was happening. Somehow, I've now got it to

I gutted the generated user logic portion of code and added my registers, so I have enough. It was the enable signals that weren?t working for the higher numbered registers. In the end, I found that it was easier to work around this issue by doing the address decoding in my own logic. I also found it easier to directly connect my interrupt signal to the output as opposed to passing it to the IPIF block, which never allowed the signal to pass through, even though it was set-up to do so. If I had more time, I would write my own as I found Xilinx's code to be an utterly disappointing and dysfunctional rat's nest.

---Matthew Hicks