Field-Programmable Gate Arrays

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ise timing analysis + different clock domains

hi since i'm pretty new ise i have a couple questions regarding timing: currently i'm working on a design for an spi in...
3 comments posted 18yrs
posted by u_stadler
3 comments posted 18yrs posted by u_stadler

Using DDR RAM on XUP V2Pro board

Hello, I'd like to ask if there's a way to get the DDR RAM on the XUP V2Pro board by Digilent up and running without us...
4 comments posted 18yrs
posted by marek.kraft
4 comments posted 18yrs posted by marek.kraft

Pipelining of FPGA code

Hi, I am trying to understand what Pipelined designing/architecture for FPGA's mean ? I went through documents which li...
5 comments posted 18yrs
posted by dhavalrules
5 comments posted 18yrs posted by dhavalrules

EDK 9.2 Woes

I updated to EDK 9.2 primarily b/c we are building a new project and I wanted the latest MPMC3 core. Here are some thin...
2 comments posted 18yrs
posted by mottoblatto
2 comments posted 18yrs posted by mottoblatto

EDK IPIF development workflow

I am new to EDK (but not ISE) and have some questions about the workflow for developing a custom IPIF peripheral. The d...
2 comments posted 18yrs
posted by AntonKowalski
2 comments posted 18yrs posted by AntonKowalski

Hand solder that FPGA on your prototype

Hi all, I've just finished constructing a new site that has web videos of soldering techniques, including how to hand s...
5 comments posted 18yrs
posted by tony
5 comments posted 18yrs posted by tony

Drawing timing-diagrams for documentation

Hi *, just stumbled across this opensource-thingy and thought it might be useful to others as well: http://drawtiming.so...
2 comments posted 18yrs
posted by news_nov07
2 comments posted 18yrs posted by news_nov07

Asynchronous FIFO and almost empty - bug?

Hi, we are using an asynchronous FIFO to bridge two clock domains. Both domains have "the same" clock speed but differe...
9 comments posted 18yrs
posted by heinerlitz
9 comments posted 18yrs posted by heinerlitz

Cascaded DCMs with variable phase shift (Xilinx)

Hi all, I'm using a Spartan-3 XC3S400 with cascaded DCMs. 1st DCM is configured as variable phase shift with 27MHz cloc...
3 comments posted 18yrs
posted by cesteban75
3 comments posted 18yrs posted by cesteban75

ISE WARNING Xst:647

Hi, I have a design that works fine in Quartus. In the process of porting it to ISE, I'm getting a series of these warn...
10 comments posted 18yrs
posted by markm
10 comments posted 18yrs posted by markm

Quartus memory init file

Hi, I've instantiated some quartus memory in VHDL using the init_file generic to specify an intel hex file. This works...
4 comments posted 18yrs
posted by markm
4 comments posted 18yrs posted by markm

System ACE debug

I am not able to load the bit file from the compact flash card to V5. It goes through the system ACE asic. We also have...
0 comments posted 18yrs
posted by cpandya
0 comments posted 18yrs posted by cpandya

FPGA not in boundary scan

Hi I am using Impact and Xilinx Multilinx cable to communicate to my FPGA board. I was able that the connection to the...
7 comments posted 18yrs
posted by Mike
7 comments posted 18yrs posted by Mike