we are using an asynchronous FIFO to bridge two clock domains. Both domains have "the same" clock speed but different clock oscillators.
We shift data phits in the FIFO which always form a data packet. In between a packet data is shifted in continously without a break. Breaks (no shift in) are only allowed in between packets. On the output side of the FIFO we need a steady data stream during a data packet. The packet may not be interrupted. As the input side may be slower we start shift-out data if at least two data phits are in the FIFO. As the 2 clocks have almost the same frequency this guarantees that we never have a buffer underflow.
The problem we found is that the almost empty flag is only asserted if the FIFO is beeing emptied and not if it is beeing filled. So if the FIFO was empty and we get a shift in the almost empty is not asserted although we set the treshold to one. Is this a bug?
We tried to solve that problem by generating a delay-empty signal at the output which guarantees that if the FIFO was emtpy and than receives a shift in we still wait another cycle so we get another shift in to avoid underflow.
This solution however does not solve the problem if the FIFO exactly had one entry when starting to shift out a packet. In this case neither delayed-empty nor almost empty is asserted, hence we get an underflow.
Why isn't the almost empty signal asserted every time there is a single packet in the FIFO? Ideas?