Field-Programmable Gate Arrays

Gnd plane coupling with DDR routing from FPGA <-> DDR?

Hopefully some of you guys who have gone through this can comment... We're doing our first board with a couple of DDRs...

39 comments posted 18yrs

posted by nial*REMOVE_THIS*

39 comments posted 18yrs posted by nial*REMOVE_THIS*

SLICEL : 92%,SLICEM 2%

PAR failed because "unable to find location..." Sounds like I'm out of SLICEL . Reports said SLICEL : 92%,SLICEM 2%, ot...

1 comments posted 18yrs

posted by wxy0624

1 comments posted 18yrs posted by wxy0624

DDR2 controler

Hello, I am currently using the DDR2 controler from XILING (under MIG1.72) for a VIRTEX4. I am encountering a problem o...

2 comments posted 18yrs

posted by bhb22l

2 comments posted 18yrs posted by bhb22l

I/O short circuit protection?

On the Spartan-3 with Vcco at 3.3V in LVTTL mode if I want to protect the outputs from possible miswiring to GND or +3....

4 comments posted 18yrs

posted by posedge52

4 comments posted 18yrs posted by posedge52

Behavioral Simulation working but Post-route Simulation is not.

Hi, I have been working on a project and get the coding done and tested using Behavioral Simulation. However, I downloa...

4 comments posted 18yrs

posted by andyto

4 comments posted 18yrs posted by andyto

device utilization

Hi all, I am little confused with naming of different family devices.....In vertex V which i should consider as number...

0 comments posted 18yrs

posted by fazulu.vlsi

0 comments posted 18yrs posted by fazulu.vlsi

What tools do you use ? Why ?

Hello all, can you please tell us what tools you prefer? Please give some arguments, why you like them. I currently use...

7 comments posted 18yrs

posted by psihodelia

7 comments posted 18yrs posted by psihodelia

area group constraint problem

Hello together, in my vhdl design for ISE 9.2 I want to partition the component instances of the submodules in my tople...

4 comments posted 18yrs

posted by l.s.rockfan

4 comments posted 18yrs posted by l.s.rockfan

Xilinx IO leakage when not powered

HI I have a Xilinx Spartan3e IO pin connected to a system bus signal. The system bus signal can be active (3.3v/0v) eve...

2 comments posted 18yrs

posted by dipumisc

2 comments posted 18yrs posted by dipumisc

What's the difference for VHDL code between simulation and synthesis?

Hi, The following is from Xilinx "Synthesis and Simulation Design Guide". Could you give me an example to show their di...

38 comments posted 18yrs

posted by rxjwg98

38 comments posted 18yrs posted by rxjwg98

Fedora 8 and ISE 9.2

Hi, I am trying to install ISE 9.2 on a Fedora 8 machine, but have numerous problems. Is there anyone that managed to do...

4 comments posted 18yrs

posted by michael_laajanen

4 comments posted 18yrs posted by michael_laajanen

CPU design uses too many slices

Hi, currently I am designing (as an amateur project) a 32bit Stack oriented CPU with two stack-pointers (Data Stack/Ret...

19 comments posted 18yrs

posted by jboehm

19 comments posted 18yrs posted by jboehm

Xilinx Multilink Connection not working

Hi I have a Xilinx Multilink cable that I would like to use to communicate with a Xilinx VirtexII that is hosted on a P...

2 comments posted 18yrs

posted by Patrick.Bateman23

2 comments posted 18yrs posted by Patrick.Bateman23

Global Reset using Global Buffer

Hello Group I=B4ve read a lot about resets and I=B4ve decided that for my designs, an asynchronous solution with a sync...

27 comments posted 18yrs

posted by rgamer1981

27 comments posted 18yrs posted by rgamer1981

yet another Altera Cyclone II EP2C35 dev. board

I've made another Cyclone II development board: english user manual : http://fpga-dev.de/docs/cyclone2_user_manual_eng....

4 comments posted 18yrs

posted by fpga-dev

4 comments posted 18yrs posted by fpga-dev