Latest threads in Field-Programmable Gate Arrays

FPGA not in boundary scan

Hi I am using Impact and Xilinx Multilinx cable to communicate to my FPGA board. I was able that the connection to the...

7 18yrs

Mike

7 18yrs Mike

Adding Desing to an Xilins Platform Studio project

Hi, I'm trying to add an existing project which successfully synthesized and simulated with ISE 8.2 and Modelsim to an...

0 18yrs

timo.g

0 18yrs timo.g

Gnd plane coupling with DDR routing from FPGA <-> DDR?

Hopefully some of you guys who have gone through this can comment... We're doing our first board with a couple of DDRs...

39 18yrs

nial*REMOVE_THIS*

39 18yrs nial*REMOVE_THIS*

SLICEL : 92%,SLICEM 2%

PAR failed because "unable to find location..." Sounds like I'm out of SLICEL . Reports said SLICEL : 92%,SLICEM 2%, ot...

1 18yrs

wxy0624

1 18yrs wxy0624

DDR2 controler

Hello, I am currently using the DDR2 controler from XILING (under MIG1.72) for a VIRTEX4. I am encountering a problem o...

2 18yrs

bhb22l

2 18yrs bhb22l

I/O short circuit protection?

On the Spartan-3 with Vcco at 3.3V in LVTTL mode if I want to protect the outputs from possible miswiring to GND or +3....

4 18yrs

posedge52

4 18yrs posedge52

Behavioral Simulation working but Post-route Simulation is not.

Hi, I have been working on a project and get the coding done and tested using Behavioral Simulation. However, I downloa...

4 18yrs

andyto

4 18yrs andyto

device utilization

Hi all, I am little confused with naming of different family devices.....In vertex V which i should consider as number...

0 18yrs

fazulu.vlsi

0 18yrs fazulu.vlsi

What tools do you use ? Why ?

Hello all, can you please tell us what tools you prefer? Please give some arguments, why you like them. I currently use...

7 18yrs

psihodelia

7 18yrs psihodelia

area group constraint problem

Hello together, in my vhdl design for ISE 9.2 I want to partition the component instances of the submodules in my tople...

4 18yrs

l.s.rockfan

4 18yrs l.s.rockfan

Xilinx IO leakage when not powered

HI I have a Xilinx Spartan3e IO pin connected to a system bus signal. The system bus signal can be active (3.3v/0v) eve...

2 18yrs

dipumisc

2 18yrs dipumisc

What's the difference for VHDL code between simulation and synthesis?

Hi, The following is from Xilinx "Synthesis and Simulation Design Guide". Could you give me an example to show their di...

38 18yrs

rxjwg98

38 18yrs rxjwg98

Fedora 8 and ISE 9.2

Hi, I am trying to install ISE 9.2 on a Fedora 8 machine, but have numerous problems. Is there anyone that managed to do...

4 18yrs

michael_laajanen

4 18yrs michael_laajanen

CPU design uses too many slices

Hi, currently I am designing (as an amateur project) a 32bit Stack oriented CPU with two stack-pointers (Data Stack/Ret...

19 18yrs

jboehm

19 18yrs jboehm

Xilinx Multilink Connection not working

Hi I have a Xilinx Multilink cable that I would like to use to communicate with a Xilinx VirtexII that is hosted on a P...

2 18yrs

Patrick.Bateman23

2 18yrs Patrick.Bateman23

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