I'm using a Spartan-3 XC3S400 with cascaded DCMs.1st DCM is configured as variable phase shift with 27MHz clock from an external VCXO in CLKIN. It is fedback (1X) from CLK0 through an IOB (run out of BUFG). This IOB's output feeds second DCM's CLKIN. First DCM's CLKFX output is also used for other tasks (multiplied by 4). 2nd DCM simply uses CLK0 and CLKFX (multiplied by 10) outputs with BUFG for both of them and the proper feedback 1X from CLK0. Attributes for both DCMs: FACTORY_JF =3D> X"8080" STARTUP_WAIT =3D> FALSE
This structure above is instantiated twice, so I use the 4 DCM of my FPGA. Both instantiations are identical.
The result of this is that one instantiation works perfectly, but the other one not. This one successes to set most phase-shift values, but fails just to set negative phase-shifts (PSINCDEC=3D0) in the range between 20 and 28 (nr. of pulses of PSCLK while PSEN is high). The rest of the phase-shifts are achieved OK. When it fails the DCM's lock and status bits do not indicate any error situation but ALL the clocks generated within the FPGA from the VCXO start to move their edges of the clock pulses pretty much (even clocks not generated by DCM).
I reset DCMs as Xilinx advises (waiting the lock of the 1st DCM to reset the second one). Has any of you experienced some similar behaviour?