1. Home
  2. Field-Programmable Gate Arrays
  3. Pipelining of FPGA code

Pipelining of FPGA code

Hi,

I am trying to understand what Pipelined designing/architecture for FPGA's mean ?

I went through documents which list all the benefits of using pipelining for FPGA's. But, none of them explicitly explained how pipelined architecture was better (efficiency-wise) against a non- pipelined architecture. I would'nt generally ask such kind of questions in a forum. But going through books on Verilog (Samir Palnitkar's)and searching in Google didnt help me.

It would help me if someone could point to some article / book / example (and preferably a Verilog based one) which explains pipelining at in depth.

I did post in the Verilog group, but from the response, I thought that the problem is more FPGA focussed.

Thanks.

Shah.

Reply to
dash82
Loading thread data ...

Pipelining means simply to take a clock cycle (or more) to produce a result. What this essentially does is to spread out a computation so that part of it gets done in one clock cycle, another part gets done in some other clock cycle. The reason you would do such a seemingly counterproductive thing is because sometimes the time it takes to do the entire calculation would mean that the system clock would have to slow down. By breaking the problem into smaller chunks, each chunk can be done faster.

No, pipelining has nothing to do with VHDL, Verilog, FPGAs or ASICs....it is a basic design technique applicable to any digital design.

KJ

Reply to
KJ

For a definition oriented towards computing architecture, se

formatting link

More generally, by putting sets of registers into a combinatorial logi function, the containing system can be run at a faster clock rate, bu takes more clock cycles. The "art" is in determining when this i appropriate, and how many stages is optimal. My consultancy rate i GBPmany/hour.

Reply to
RCIngham

KJ wrote: (snip)

This is especially convenient with FPGAs which usually have a FF at the output of each LUT.

Assuming that you have a register, a big complicated block of logic, followed by another register, pipelining allows you to speed up the clock by adding additional registers inside the block of logic.

One point, though. Pipelining allows an increased throughput, though usually at increased latency. If you only want one it won't help speed it up. It is when you want more than one that it helps. The first result comes out after N (number of pipeline stages) clock cycles. After that results come out each cycle.

-- glen

Reply to
glen herrmannsfeldt

Thank you !

Reply to
dash82

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.