Using DDR RAM on XUP V2Pro board

Memory interface gererator 007 provides DDR1 SDRAM and DDR2 SDRAM memory interfaces for xilinx Virtex2, Virtex2P and Spartan3 FPGAs.It generates design files(rtl,sdc,ucf ) and documents (Timing,appnotes, user guide) in the usr folder for the selected options from the GUI.

Following steps generate DDR1 SDRAM memory interface for, Components, 8 DQs per DQS, right side of V2P device to 72 bit data.

• Select Memory type DDR1 by clicking the down arrow button.

• Select the Components by checking the Component radio buttons.

• Select the number of DQ bits per DQS 8 by checking the X8 radio buttons.

• Select Family Virtex2P by clicking the down arrow button.

• Select Part 2vp20ff1152 by clicking the down arrow button.

• Select the Speed grade -6 by clicking the button.

• Select the Frequency in MHz 200 by dragging the slider.

• Select the number of controllers to 1 by clicking the down arrow button.

• Select the banks for data and datastrobe by clicking the check box 2 and

• Select the banks for address & control by clicking the check box 6 and 7.

• Enter the WASSO values for banks 2 and 3 by clicking the WASSO Table, if the WASSO values differ from default values.

• Select the Data bits 72 by clicking the down arrow button.

• To exclude Vrp/Vrn pins for memory interface check the "Reserve Vrp/Vrn pins " box.

• From Menu "Options", HDL, select Verilog or VHDL.

• From Menu "Options", Design, select Full controller or Physical layer with data or Physical layer with data, address and control.

• Click on Show pins.The pins from the selected banks are displayed in the "Selected pins" listbox. To reserve some pins,double click it. Also click on "Read reserve pin ucf" button to input your constraint file so that the pins will not be used for memory interface.

• Add button allows the user to add the pins back from the Reserved pins list for allocating to memory interface.

• Hierarchy path provides the user for instantiating memory interface with other designs.

• By default result files are stored in ../usr directoy. Result directory button allows the user to save the result files to a selected directory.

• Click on "Generate design" to generate the design files.The files are created in usr directory.

• Pin compatibility check button allows to generate UCF files across multiple devices.

• Pin editor option allows the user to select the dq, dqs and no_dpin pins. Click on Show pins activates the Pin editor.

Believe it or not, I've already read it. I just wanted to ask if there are any surprises that might happen along the way. Sometimes things don't work exactly as they should. It's better to know about it earlier than after two weeks of why-the-hell-desn't-it-work. If anyone can give me such directions, has implemented successful controller on this board using MIG, or even points out an alternative solution that will work for me - that would be great. I am not working on it during the weekend, so I just thought it would be a good thing to ask.

Kind regards,

Marek.

I took a look at using the mig generated core for DDR ram on a V2P. I discovered that in the user interface generated by that tool, some signals are clocked on the system clock, some on a 90 degree phase shifted clock, and some on a 180 degree phase shifted clock. Yikes! So much for an "easy" interface.

I abandoned any attempt to use that core, and instead hacked on the plb ddr core, simply ignoring the plb interface and adding my own user interface instead.

Make sure you dont use the DCM and you have to complete the UCF, as for some reason Xilinx never produced a MIG tool for their V2P board (!) and then your nearly there, but ours doesn't work yet either so do keep in touch.