Field-Programmable Gate Arrays

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Pin assignment with Quartus II for PCB placement

Hey folks, I'm working on a PCB that will have an Altera FPGA (Cyclone II in 672 ball FBGA). There is no code to be loa...
6 comments posted 18yrs
posted by srpenney
6 comments posted 18yrs posted by srpenney

virtex II pro - own core on plb with 2 interrupts

Hi, I'am trying to set up an Interface for an A/D - D/A Codec on an virtex II pro plattform using the (ppc) plb bus. Wh...
1 comments posted 18yrs
posted by sven.artz
1 comments posted 18yrs posted by sven.artz

selecting FPGA

I'm relatively new to FPGA. I've learnt vhdl and done few designs in xilinx Spartan II fpga, xsa v1.2 board. I've been...
2 comments posted 18yrs
posted by bisheshkh
2 comments posted 18yrs posted by bisheshkh

usb cable driver

Hi All, I have a XupV2P board, ISE 9.1 and Windows Vista. I can't find the right driver for my USB cable to download my...
6 comments posted 18yrs
posted by andre
6 comments posted 18yrs posted by andre

SDRAM and S3E - is the example broken?

Did anyone get the DDR SDRAM work on the Xilinx Spartan 3E Starter board? I have tried to load the pre-built BIT file s...
1 comments posted 18yrs
posted by alexf
1 comments posted 18yrs posted by alexf

For God's sake !! It did not work at all !!!

Hello buddies, I loved surely all of you have written herein and hence, I would like to thank everyone of you. BUT, I a...
3 comments posted 18yrs
posted by matadouros.home
3 comments posted 18yrs posted by matadouros.home

Seeking help on xilkernel

I'm using a version of XMK provided by Avnet, for Memec Virtex-4 FX12 LC Evaluation Board. It includes a xilkernel demo...
0 comments posted 18yrs
posted by hkxforce
0 comments posted 18yrs posted by hkxforce

student requiring assistance :)

I'm a final yr student undertaking a project which requires a microcontroller with an operating clk freq at 60MHz. My u...
5 comments posted 18yrs
posted by truongt1024
5 comments posted 18yrs posted by truongt1024

Using FSL with Interrupts

Hi all , Is it possible to use FSL read on an interrupt basis rather than polling? I have a scenario where i only want...
2 comments posted 18yrs
posted by niladri1979
2 comments posted 18yrs posted by niladri1979

Synplify .sdc file

Hi, Is it possible to define clocks in the .sdc file of a design, while those clocks only appear in a peripheral or a co...
1 comments posted 18yrs
posted by wei.wang.cantab
1 comments posted 18yrs posted by wei.wang.cantab

Spartan-3E starter kit, USB Jtag

I recall someone had figured out the schematics of the builtin USB based Jtag programmer on the Xilinx/Digilent Spartan...
0 comments posted 18yrs
posted by posedge52
0 comments posted 18yrs posted by posedge52