I'm working on a PCB that will have an Altera FPGA (Cyclone II in 672 ball FBGA). There is no code to be loaded to the FPGA yet so it makes testing the pin assignment hard (impossible?). On the PCB I'm planning to have a 256Mb of DDR SDRAM (16-bit wide DQ bus). I'm concerned that some of my other signals to and from the FPGA may cause problems with the DDRA SDRAM lines. What I was hoping to do was open up Quartus II and assign my pins for given directions, drive strengths, IO standards etc. The run the assignment checking tool to see if any of the signals were brought in on pins that are not acceptable. Does anyone know how to do this kind of testing when there is no RTL code driving the pins (yet)?
Create a 'dummy' design. Use all of the same signal names and signal directions (in/out/inout) that will be on the final FPGA design. Make up any sort of dummy logic that uses all of the inputs to drive all of the outputs and inouts. Run it through Quartus and make sure that it doesn't generate any warnings about inputs that are not used or outputs that are driven to a constant. Now you have something that you do pin placement on and from that point simply run the I/O assignment analysis every now and then as you get pins assigned, Quartus will complain if you have any errors.
About the only considerations you'll need to make in creating the dummy logic has to do with clocks and PLLs. Make sure that any input clocks that will be connected to flip flops at least clock in 'something' in your dummy logic. If you'll be using PLLs instantiate them and configure them for the estimated design frequency that you intend to run it at, and if those PLL outputs will be driving output pins (like the DDR clock as an example) make sure the PLL output is connected to the appropriate output signal. By doing this, Quartus will generate errors or warnings when running the I/O assignment analysis if you try to do something that you shouldn't or can't do.
Lastly, since you're using some form of DDR controller, refer to the Altera documentation on the preferred pins to use for the controller I/ O otherwise you may have trouble getting the proper DDR performance that you need for your project. Quartus won't generate any warnings about this ('specially since the dummy logic won't have any DDR controller), you'll have to manually check it.
I agree wholeheartedly, unfortunately I'm not being given much of a choice. The RAM interface isn't absolutely crucial though, it's a "nice to have". So if I end up not being able to use it it's not the end of the world.
Thanks for the reply. I'd only been looking at the FPGA documentation, clearly I overlooked the Quartus documentation, which was a mistake. This looks to be much more useful than what I was working with.
Thanks a lot, it's funny that I get answers from someone on Altera through a forum faster than my service requests.
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