Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)

In UCF I write: NET "RefClkp" LOC = "AB4" | IOSTANDARD = "LVDS_25" ; NET "RefClkn" LOC = "AB3" | IOSTANDARD = "LVDS_25" ;

In project: IBUFDS ref_clk_buffer (Test, RefClkp, RefClkn);

But ISE swear in mapping:

ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB component: PAD symbol "2RefClkn" (Pad Signal = RefClkn) SlaveBuffer symbol "ref_clk_buffer/SLAVEBUF.DIFFIN" (Output Signal = ref_clk_buffer/SLAVEBUF.DIFFIN) Each of the following constraints specifies an illegal physical site for a component of type IOB: Symbol "RefClkn" (LOC=AB3 [Physical Site Type = IPAD]) The component type is determined by the types of logic and the properties and configuration of the logic it contains. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint. Please correct the constraints accordingly. ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB component: PAD symbol "RefClkp" (Pad Signal = RefClkp) DIFFAMP symbol "ref_clk_buffer/IBUFDS" (Output Signal = Test_OBUF) Each of the following constraints specifies an illegal physical site for a component of type IOB: Symbol "RefClkp" (LOC=AB4 [Physical Site Type = IPAD]) The component type is determined by the types of logic and the properties and configuration of the logic it contains. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint. Please correct the constraints accordingly.

In UG196 (v1.3) May 25, 2007 I see in page 51 that: This section shows key elements of a UCF that instantiates seven GTP_DUAL tiles. The file implements the example configuration shown in Figure 5-5, page 71. The device and package combination chosen in this example is an XC5VLX110T-FF1136. ; ; Instantiate the GTP_DUAL tiles in locations X0Y7 to X0Y1 ; INST design_root/gtp_dual[1]/gtp_dual LOC=GTP_DUAL_X0Y1; INST design_root/gtp_dual[2]/gtp_dual LOC=GTP_DUAL_X0Y2; INST design_root/gtp_dual[3]/gtp_dual LOC=GTP_DUAL_X0Y3; INST design_root/gtp_dual[4]/gtp_dual LOC=GTP_DUAL_X0Y4; INST design_root/gtp_dual[5]/gtp_dual LOC=GTP_DUAL_X0Y5; INST design_root/gtp_dual[6]/gtp_dual LOC=GTP_DUAL_X0Y6; INST design_root/gtp_dual[7]/gtp_dual LOC=GTP_DUAL_X0Y7; ; ; Connect the REFCLK_PAD_(N/P) differential pair to the middle ; GTP_DUAL tile (GTP_DUAL_X0Y4) ; NET refclk_pad_n LOC=P4; NET refclk_pad_p LOC=P3; The instantiation of the GTP_DUAL tiles and the IBUFDS primitive is typically done in HDL code within the design hierarchy. That code also connects the output of the IBUFDS primitive to the CLKIN inputs of the GTP_DUAL tiles, as illustrated by the following Verilog code fragment: // // Instantiate the GTP_DUAL tiles // genvar tile_num; generate for (tile_num = 1; tile_num

Reply to
axalay
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If this clock I may use only in GTP_DUAL?

Reply to
axalay

A couple of comments on this:

1) You have given an incomplete description of your problem as you did not specify which part/package was being used. After looking through all of the package files the only possible on with AB3/AB4 is a FF665. If you are using another package that these locations are not valid.

2) The MGTREFCLK inputs do not have alternative standards so you should not attach a IOSTANDARD=LVDS_25 in the UCF constraint.

3) IMHO, you should always use .PORT mappings when instantiating a module in Verilog to ensure that the you do get the right NET to PORT connection.

4) The only allowed connection from the MGT REFCLK pins is to a GTP_DUAL CLKIN pin. You can not be routed this to any other source. You can use the REFCLKOUT pin from the GTP_DUAL to pass the signal through to the fabric resources.

Ed McGettigan

-- Xilinx Inc

Reply to
Ed McGettigan

So the clock to the GTPs does always have to be LVDS_25, no LVPECL supported directly, like in the "regular" IOs? So I guess I need external termination resistors like described in xapp696 if I want to use a LVPECL clock source for the MGTs?

cu, Sean

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Reply to
Sean Durkin

Thanks.

  1. Yes-I am use FF665 package
  2. This clock is LVDS (UG196 (325mV) AC-coupled
  3. If I write in UCF " INST "serdes/gtpdual1/gtp_dual" LOC = "GTP_DUAL_X0Y1" ; ", may I do not write in UCF MGTREFCLK pin locations?
  4. I find what You say in UG196 (v1.3) May 25, 2007

Now I have nex question: ISE give error in Design Hierarchy Analysis: ERROR:HDLCompilers:87 - "XXX.v" line 33 Could not find module/ primitive 'gtpdualxxx'

What files he do not find? I am understand that: I must write directory, where ISE may search this files in Syntesis Option/Verilog Include Directories. But I dont now - what files he whant....

Reply to
axalay

The MGT REFCLK inputs must be AC coupled and there is an internal bias for optimal performance. This means that either LVDS or LVPECL can be used as inputs so long as the voltage swings comply with Table 17 in the Virtex-5 data sheet:

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Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

Your error message is specific to your HDL implementation as the only simulation primitive model that is provided is the GTP_DUAL smartmodel/swift model. There is a chance that you have not correctly installed the GTP_DUAL models, but this should not result in the error message that you are reporting.

I would strongly suggest that you use the CoreGen GTP Wizard to create your GTP module. You should run the example implementation top level design through simulation, synthesis and ISE so that you have a known good implementation that you can base your own design work on.

BTW: The latest UG196 GTP User Guide is V1.4 Sept 12, 2007

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

Thanks! I solve this problem

Reply to
axalay

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