In UCF I write: NET "RefClkp" LOC = "AB4" | IOSTANDARD = "LVDS_25" ; NET "RefClkn" LOC = "AB3" | IOSTANDARD = "LVDS_25" ;
In project: IBUFDS ref_clk_buffer (Test, RefClkp, RefClkn);
But ISE swear in mapping:
ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB component: PAD symbol "2RefClkn" (Pad Signal = RefClkn) SlaveBuffer symbol "ref_clk_buffer/SLAVEBUF.DIFFIN" (Output Signal = ref_clk_buffer/SLAVEBUF.DIFFIN) Each of the following constraints specifies an illegal physical site for a component of type IOB: Symbol "RefClkn" (LOC=AB3 [Physical Site Type = IPAD]) The component type is determined by the types of logic and the properties and configuration of the logic it contains. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint. Please correct the constraints accordingly. ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB component: PAD symbol "RefClkp" (Pad Signal = RefClkp) DIFFAMP symbol "ref_clk_buffer/IBUFDS" (Output Signal = Test_OBUF) Each of the following constraints specifies an illegal physical site for a component of type IOB: Symbol "RefClkp" (LOC=AB4 [Physical Site Type = IPAD]) The component type is determined by the types of logic and the properties and configuration of the logic it contains. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint. Please correct the constraints accordingly.
In UG196 (v1.3) May 25, 2007 I see in page 51 that: This section shows key elements of a UCF that instantiates seven GTP_DUAL tiles. The file implements the example configuration shown in Figure 5-5, page 71. The device and package combination chosen in this example is an XC5VLX110T-FF1136. ; ; Instantiate the GTP_DUAL tiles in locations X0Y7 to X0Y1 ; INST design_root/gtp_dual[1]/gtp_dual LOC=GTP_DUAL_X0Y1; INST design_root/gtp_dual[2]/gtp_dual LOC=GTP_DUAL_X0Y2; INST design_root/gtp_dual[3]/gtp_dual LOC=GTP_DUAL_X0Y3; INST design_root/gtp_dual[4]/gtp_dual LOC=GTP_DUAL_X0Y4; INST design_root/gtp_dual[5]/gtp_dual LOC=GTP_DUAL_X0Y5; INST design_root/gtp_dual[6]/gtp_dual LOC=GTP_DUAL_X0Y6; INST design_root/gtp_dual[7]/gtp_dual LOC=GTP_DUAL_X0Y7; ; ; Connect the REFCLK_PAD_(N/P) differential pair to the middle ; GTP_DUAL tile (GTP_DUAL_X0Y4) ; NET refclk_pad_n LOC=P4; NET refclk_pad_p LOC=P3; The instantiation of the GTP_DUAL tiles and the IBUFDS primitive is typically done in HDL code within the design hierarchy. That code also connects the output of the IBUFDS primitive to the CLKIN inputs of the GTP_DUAL tiles, as illustrated by the following Verilog code fragment: // // Instantiate the GTP_DUAL tiles // genvar tile_num; generate for (tile_num = 1; tile_num