SDRAM and S3E - is the example broken?

Did anyone get the DDR SDRAM work on the Xilinx Spartan 3E Starter board?

I have tried to load the pre-built BIT file specifically for this board: s3e_starter_revD_mig_ddr. The readme file states that the LED1 should be slightly lit while LED0 should be OFF. In my case the LED1 is fine, but the LED0 is constantly ON. I tried to load the ChipScope - enabled version of the bitstream and get the same result. Also the lfsr_data has nothing in common with read_data_reg in ChipScope.

I tried running on 100, 50 and even 32 MHz (should be 80-133). Same effect.

And help highly appreciated.


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Alex Freed
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Hello, I extracted the VHDL sources from the example and prepared a project for ISE 9.2 webpack. It works on my S3E rev.D with on-board 50MHz oscillator. The original bitfiles do not work here too (LEDs are off) but I don't know why :-(

You can download the ISE project with sources and bitfiles here:

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-- Jara

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