I was wondering if anyone could help me figure out one thing that is holding us up for porting some Verilog code that works for Xilinx/ISE to Lattice/Synplicity. Specifically, for Xilinx, we use metacomments like this to prevent optimization across certain bits of logic:
//synthesis attribute keep_hierarchy of mux0 is yes
Would anyone happen to know the equivalent metacomment for Lattice/ Synplicity?
I think syn_maxfan gives you your first attribute.
The equivalent_register_removal = "no" sounds like syn_preserve = 1. I haven't used XST myself, so I'm guessing by the names. Two identical flops won't be optimized to one, constant registers aren't removed, and register retiming won't affect registers where syn_preserve=1.
Thanks again for the help. What I'm finding seems to suggest that the synthesis attribute should be on the same line as the net or reg it's referring to. How do you apply more than one attribute to the same object? Like syn_preserve=1 and syn_maxfan=1 to the same register?
I thought I'd learned how to do multiple attributes from the Synplify help as well. Part of your answer may depend on whether you're Verilog or VHDL. In my Verilog use, I'll either have two attributes in the new format preceeding the object (where I think the comma is used and no "synthesis" keyword is needed)
If you want to make an attribute global for a module and its submodules, you can attach the primitive to the initial module declaration. Adding the /* synthesis xc_fast=1 */ before the closing semicolon to the declaration list applies the attribute or directive globally for that point in the hierarchy and down.